USB-PD IC Regulator with Load-Dependent Biasing and Inrush Control

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Solution Overview

Problem

Conventional USB-PD IC controllers face challenges in robust on-chip voltage regulation and inrush current limiting, requiring sophisticated designs to manage varying load currents and prevent electromigration, while balancing overdrive capability and inrush current control.

Innovation Solution

The USB-PD IC controller incorporates a regulator with an amplifier and pass transistor that adjusts current inversely proportional to the amplifier's output, a clamping circuit to limit overdrive voltage during inrush events, and an override circuit that deactivates clamping in bypass mode when current thresholds are met, ensuring efficient voltage regulation and inrush current management.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a significant amount of capacitance is provided at the regulator output node to suppress transients, then transient suppression capability is improved, but peak inrush current increases causing electromigration in metal routings

Engineering Contradiction:
Improvetransient suppression capabilityVSAvoidpeak inrush current
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent introduces an intermediary component (current limiting circuit or series resistor) between the regulator output and the load capacitor to suppress inrush current. This intermediary element limits the peak current flowing into the capacitor during transient events while still allowing the capacitor to provide adequate transient suppression, thus resolving the contradiction between reliability and harmful factors.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent applies preliminary action by pre-charging the output capacitor through a controlled path before full power connection, or by using soft-start circuitry that gradually increases the charging current. This preliminary controlled charging prevents sudden inrush current peaks that would cause electromigration, while still achieving the required transient suppression capability.

Inventive Principle:
Principle #10Preliminary action

2Speed

If the regulator supplies full overdrive capability in bypass mode, then power delivery speed is improved, but inrush current control is compromised

Engineering Contradiction:
Improvepower delivery speedVSAvoidinrush current
Core Design Contradiction:
SpeedVSObject-affected harmful factors

Solution Approach 1:

The patent implements dynamic control by making the regulator's overdrive capability adjustable based on operating conditions. The system dynamically switches between full overdrive mode (for normal power delivery) and limited overdrive mode (for inrush protection), allowing it to optimize both speed and safety depending on the situation. This is achieved through control circuitry that monitors load conditions and adjusts the regulator's drive strength accordingly.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS11658575B2Regulator architecture with load dependent biasing and inrush current control
Publication Date: 2023.05.23 INFINEON TECHNOLOGIES AMERICAS CORP
  • US11658575B2 patent drawing
  • US11658575B2 patent drawing
  • US11658575B2 patent drawing

AI summary

A USB-power delivery integrated circuit controller includes: one or more driver circuits configured to control operation of a buck-boost converter; a regulator configured to regulate an internal supply voltage of the controller from a variable input voltage of the buck-boost converter in a regulation mode, and to pass the variable input voltage as the internal supply voltage without regulation in a bypass mode, the regulator being in the bypass mode when the variable input voltage is below the internal supply voltage, the regulator including an amplifier and a pass transistor configured to pass a current that is inversely proportional to an output of the amplifier; a clamping circuit configured to limit an overdrive voltage of the pass transistor during an inrush current event; and an override circuit configured to deactivate the clamping circuit in the bypass mode when the current passed by the pass transistor is below a current threshold.