USB PHY Signal Detection Circuitry Power Management
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Solution Overview
Problem
Current USB power saving techniques, particularly in the U3 low power state, consume excessive power due to the continuous operation of signal detection circuitry for detecting low frequency periodic signals, which limits battery life in mobile devices.
Innovation Solution
The signal detection circuitry and medium speed clock within the USB PHY are powered down for most of the low speed reference clock period, only activating to sample for low frequency periodic signals, thereby reducing power consumption and maintaining low latency for returning to the active state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If signal detection circuitry operates continuously in U3 low power state, then detection reliability is maintained, but power consumption increases
Solution Approach 1:
The signal detection circuitry is activated periodically at specific intervals during the U3 low power state rather than operating continuously. The circuit wakes up at predetermined times to sample the bus for low frequency periodic signals, then returns to sleep mode. This periodic activation maintains detection capability while dramatically reducing power consumption compared to continuous operation.
Solution Approach 2:
The system dynamically transitions the signal detection circuitry between active and inactive states based on operational requirements. During U3 low power state, the circuitry remains inactive most of the time and only becomes active periodically when needed for signal sampling. This dynamic state management optimizes the balance between detection reliability and power consumption.
2Use of energy by moving object
If signal detection circuitry is powered down, then power consumption decreases, but detection latency increases
Solution Approach 1:
The system performs preliminary actions by pre-scheduling wake-up times and signal sampling intervals before entering the U3 low power state. The signal detection circuitry is configured to activate at predetermined intervals, ensuring that detection opportunities are prepared in advance. This preliminary arrangement minimizes detection latency while maintaining power savings, as the circuit knows exactly when to wake and sample without requiring continuous monitoring.
Data Source
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AI summary
Power saving systems and methods for Universal Serial Bus (USB) systems are disclosed. When a USB physical layer (PHY) enters a U3 low power state, not only are normal elements powered down, but also circuitry within the USB PHY associated with detection of a low frequency periodic signal (LFPS) wake up signal is powered down. A low speed reference clock signal is still received by the USB PHY, and a medium speed clock within the USB PHY is activated once per period of the low speed reference clock signal. The medium speed clock activates the signal detection circuitry and samples a line for the LFPS. If no LFPS is detected, the signal detection circuitry and the medium speed clock return to low power until the next period of the low speed reference clock signal. If the LFPS is detected, the USB PHY returns to a U0 active power state.