USB 2 Repeater Circuit for EOP Hold and Dribble Bit Compliance
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Solution Overview
Problem
Existing USB repeaters face challenges in supporting EOP bit width and dribble bits compliance without using CDR or PLL, which increases footprint and power consumption, making them unsuitable for smaller, lower-power environments.
Innovation Solution
A circuit and system design that includes amplifiers, comparators, and a logic circuit to detect idle differential input signals and maintain the last bit of the EOP indicator for up to four additional bits, preventing noise transmission without relying on CDR or PLL, thereby supporting EOP detection and dribble bits compliance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If CDR or PLL is used for EOP detection and dribble bits compliance, then detection precision is improved, but device footprint and power consumption increase
Solution Approach 1:
The patent extracts the EOP detection function from the complex CDR/PLL system and implements it using a dedicated comparator circuit that directly compares the differential input signal to a reference voltage. This extraction eliminates the need for expensive CDR/PLL circuits while maintaining detection precision, directly resolving the contradiction between measurement precision and device footprint.
Solution Approach 2:
The patent replaces the expensive, power-consuming CDR/PLL components with a simple, low-cost comparator circuit. This substitution uses a much simpler electronic component (comparator) that consumes significantly less power and occupies minimal footprint, while still achieving the required EOP detection precision for USB 2.0 compliance.
2Measurement precision
If CDR or PLL is used for EOP detection and dribble bits compliance, then detection precision is improved, but power consumption increases
Solution Approach 1:
The patent extracts the EOP detection function from the power-consuming CDR/PLL system and implements it using a dedicated comparator circuit. This extraction eliminates the high power consumption associated with CDR/PLL operations while maintaining detection precision, directly resolving the contradiction between measurement precision and power consumption.
Solution Approach 2:
The patent replaces the expensive, power-consuming CDR/PLL components with a simple, low-power comparator circuit. This substitution dramatically reduces power consumption while maintaining the required EOP detection precision, making the repeater suitable for battery-powered and energy-constrained applications.
3Use of energy by stationary object
If the transmitter is disabled immediately after EOP detection, then power consumption is reduced, but dribble bits compliance is violated
Solution Approach 1:
The patent implements preliminary action by detecting the EOP condition in advance using the comparator circuit, then activating the bus holder circuit to maintain the last valid data state on the differential lines. This preliminary holding action allows the transmitter to be disabled after the EOP is detected and held, ensuring dribble bits compliance (preventing noise transmission) while still achieving power savings by controlling the transmitter shutdown timing.
Solution Approach 2:
The patent introduces the bus holder circuit as an intermediary between the comparator detection and the transmitter output. This intermediary component holds the last valid data state on the differential lines after EOP detection, acting as a buffer that allows the transmitter to be disabled while maintaining signal integrity and preventing noise transmission, thus ensuring dribble bits compliance.
4Reliability
If the bus holder circuit is used to maintain the last bit, then dribble bits compliance is improved, but device complexity increases
Solution Approach 1:
The bus holder circuit is designed to serve multiple functions: it holds the last valid data state on the differential lines, prevents noise transmission during transmitter shutdown, and maintains signal integrity for USB 2.0 compliance. By consolidating these multiple functions into a single circuit block, the patent improves dribble bits compliance without proportionally increasing device complexity.
Data Source
AI summary
Aspects of the disclosure provide for a method. In at least some examples, the method includes receiving, at a circuit, data via a differential input signal. The method further includes detecting a falling edge in the data received via the differential input signal. The method further includes holding an output of the circuit at a final logical value of the data. The method further includes disabling a transmitter of the circuit while holding the output of the circuit at the final logical value of the data. The method further includes releasing the output of the circuit from the final logical value of the data.