USB Host Scheduler Circuit Reducing Memory and Power
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Solution Overview
Problem
Conventional USB host architectures require large memory and complex host controller software, leading to increased die size, power consumption, and cost, particularly in portable devices, where they are undesirable.
Innovation Solution
A communication device with a processor, memory, and a scheduler circuit that uses 'ping-pong' data structures and circular buffers to reduce memory size and processor bandwidth, allowing the scheduler circuit to operate separately from the processor to manage data transfers efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional USB host architecture is used with large memory buffering, then data transfer capability is improved, but die size increases
Solution Approach 1:
The patent segments the data transfer functionality by separating the scheduler circuit from the processor, allowing independent optimization. The scheduler circuit handles endpoint descriptor traversal and data transfer scheduling without requiring the processor to buffer large amounts of data, thus reducing memory requirements and die size while maintaining data transfer capability.
Solution Approach 2:
The scheduler circuit acts as an intermediary between the processor and the USB data transfer operations. It manages endpoint descriptors and coordinates data transfers without requiring the processor to maintain large buffers, enabling efficient data transfer with reduced memory and die size.
2Productivity
If conventional USB host architecture with complex HCD software is used, then data transfer management is improved, but power consumption increases
Solution Approach 1:
The patent extracts the data transfer scheduling functionality from the processor and HCD software, implementing it in a dedicated scheduler circuit. This hardware implementation eliminates the need for complex software management and continuous processor intervention, significantly reducing power consumption while maintaining effective data transfer management.
Solution Approach 2:
The scheduler circuit is self-sufficient in managing endpoint descriptors and coordinating data transfers without requiring active processor involvement. This autonomous operation reduces power consumption by eliminating the need for the processor to continuously execute HCD software routines.
3Productivity
If processor manages endpoint descriptors directly, then data transfer control is improved, but processor bandwidth consumption increases
Solution Approach 1:
The scheduler circuit serves as an intermediary that handles endpoint descriptor traversal and data transfer coordination, freeing the processor from these bandwidth-intensive operations. The processor only needs to interact with the scheduler circuit through simple interface signals, dramatically reducing processor bandwidth consumption while maintaining effective data transfer control.
4Productivity
If large memory is allocated for data buffering, then data transfer capacity is improved, but cost increases
Solution Approach 1:
The patent segments the data transfer function into a dedicated scheduler circuit that operates independently with minimal memory requirements. This eliminates the need for large memory allocations for data buffering, reducing component costs and simplifying manufacturing while maintaining adequate data transfer capacity through efficient scheduling.
Data Source
AI summary
A device can include a processor configured to write a first data structure to a memory, the first data structure comprising a list of at least one data channel; and a scheduler circuit comprising logic circuits responsive to the processor, the scheduler circuit configured to transfer data packets to the at least one data channel via a packet based serial data communication interface and according to the first data structure.