USB 3.0 Reference Clock Compensation for Non-Compliant PCIe Hosts
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Solution Overview
Problem
Non-compliant PCIe reference clocks, often due to overclocking or center-spread configurations, cause compatibility issues when coupled with USB 3.0 host controllers, exceeding the 5600 ppm clock difference tolerance, leading to failed USB 3.0 device operations.
Innovation Solution
A method that involves sampling data during link negotiation to determine the frequency offset between the device and host reference clocks, applying this offset to the device reference clock to create a corrected clock, allowing successful link negotiation and operation without altering the host's reference clock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the PCIe reference clock is used for USB 3.0 host controllers, then the USB 3.0 interface can be integrated into the motherboard, but the clock frequency difference may exceed the 5600 ppm limit required by USB 3.0 specification
Solution Approach 1:
The patent changes the clock frequency parameter by measuring the actual PCIe reference clock frequency and adjusting the USB 3.0 device's local reference clock accordingly. This dynamic parameter adjustment ensures the clock difference remains within the 5600 ppm USB 3.0 specification limit, resolving the contradiction between interface integration and operational reliability
Solution Approach 2:
The patent implements a feedback mechanism where the USB 3.0 device measures the PCIe reference clock frequency, calculates the frequency offset, and uses this information to adjust its local reference clock. This closed-loop feedback ensures continuous compliance with USB 3.0 clock accuracy requirements despite variations in the host's PCIe clock
2Object-affected harmful factors
If a center-spread reference clock is used to avoid electromagnetic compatibility issues, then EMC problems are reduced, but the clock frequency may deviate more from the nominal rate causing USB 3.0 compatibility issues
Solution Approach 1:
The patent uses feedback by continuously monitoring the PCIe reference clock frequency and adjusting the USB 3.0 device's local reference clock based on the measured offset. This allows the system to accommodate center-spread clocks while maintaining USB 3.0 protocol compliance through dynamic compensation
Solution Approach 2:
The patent dynamically changes the local reference clock parameter in response to the host's clock characteristics. By adjusting the device's clock frequency based on measured offsets, the system maintains USB 3.0 compliance even when the host uses center-spread reference clocks that deviate from nominal rates
3Reliability
If the host reference clock is altered to comply with USB 3.0 specifications, then USB 3.0 operation is ensured, but the PCIe clock configuration and other USB 3.0 interfaces may be affected
Solution Approach 1:
The patent applies local quality by making the clock adjustment specific to the USB 3.0 device's local reference clock rather than altering the host's PCIe reference clock. This localized adjustment ensures USB 3.0 compliance without affecting the host's PCIe operations or other USB 3.0 interfaces that share the same reference clock
Solution Approach 2:
The patent segments the clock adjustment function by implementing it only in the USB 3.0 device rather than in the host. This segmentation isolates the clock compensation to where it is needed, preventing interference with PCIe and other USB 3.0 interfaces that rely on the original host reference clock
4Reliability
If manual clock adjustment is implemented to fix USB 3.0 compatibility issues, then some systems can be made to work, but user intervention is required and not all cases can be covered
Solution Approach 1:
The patent implements self-service by enabling the USB 3.0 device to automatically measure the PCIe reference clock frequency, calculate the offset, and adjust its own local reference clock without user intervention. This automated self-adjustment ensures USB 3.0 compliance across all scenarios without requiring manual configuration
Solution Approach 2:
The patent uses feedback to automatically detect and correct clock frequency issues. By continuously monitoring the reference clock and dynamically adjusting the local clock based on measured offsets, the system eliminates the need for manual intervention while ensuring USB 3.0 protocol compliance in all cases
Data Source
AI summary
In a first embodiment of the present invention, a method for operating a device having a device reference clock, in a system including a host with a host reference clock is provided, the method comprising: beginning a link negotiation stage between the device and the host using the device reference clock; during the link negotiation stage, sampling data received from the host to determine a frequency offset of the host reference clock; applying the frequency offset to the device reference clock to create a corrected device reference clock; and completing the link negotiation stage using the corrected device reference clock. This completing may include either continuing the original link negotiation stage or restarting it.