User-Level Interprocessor Interrupts Without Privilege Transitions
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing systems incur significant latency due to multiple privilege level transitions when user-level applications interact with I/O devices, exceeding the operational latency of the I/O devices themselves.
Innovation Solution
Implementing a user-level interrupt mechanism that delivers interrupts directly to user-level applications without privilege level transitions, using a user-level APIC and interrupt handler address data structure managed by the processor and operating system, allowing direct control flow modification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If interrupts are delivered through the operating system kernel with multiple privilege level transitions, then system stability and security are maintained, but software latency increases significantly
Solution Approach 1:
The interrupt delivery system is segmented into two independent paths: a traditional kernel path for system-level interrupts and a new user-level path for application-level interrupts. This segmentation allows user-level applications to receive interrupts directly without traversing the kernel, eliminating privilege level transitions while maintaining kernel stability for system-level operations.
Solution Approach 2:
The patent introduces user-level interrupt controllers and interrupt handler address data structures as intermediary components between I/O devices and user-level applications. These intermediaries enable direct interrupt delivery to userspace without requiring privilege level transitions, thus reducing latency while preserving system stability through controlled intermediary management.
2Reliability
If multiple privilege level transitions are used for interrupt delivery, then security control is maintained, but operational efficiency decreases
Solution Approach 1:
The system segments interrupt handling into kernel-managed interrupts and user-level interrupts. User-level applications can directly handle interrupts through user-level interrupt controllers without kernel intervention, eliminating multiple privilege level transitions and improving operational efficiency while maintaining security through controlled user-level execution environments.
Solution Approach 2:
The patent changes the execution environment parameter from kernel-mode to user-mode for interrupt handling. By allowing interrupts to be delivered and handled in the user-level execution environment, the system eliminates the overhead of privilege level transitions while maintaining security through the existing user-mode execution context and memory protection mechanisms.
3Device complexity
If traditional kernel-level interrupt handling is used, then system control is centralized, but interrupt processing time increases
Solution Approach 1:
The interrupt handling system is divided into kernel-level and user-level components. User-level applications implement their own interrupt controllers and handlers, eliminating the need for centralized kernel processing and reducing interrupt processing time through distributed, application-specific handling while maintaining manageable system complexity through standardized interfaces.
Data Source
AI summary
Processors, methods, and systems for user-level interprocessor interrupts are described. In an embodiment, a processing system includes a memory and a processing core. The memory is to store an interrupt control data structure associated with a first application being executed by the processing system. The processing core includes an instruction decoder to decode a first instruction, invoked by a second application, to send an interprocessor interrupt to the first application; and, in response to the decoded instruction, is to determine that an identifier of the interprocessor interrupt matches a notification interrupt vector associated with the first application; set, in the interrupt control data structure, a pending interrupt flag corresponding to an identifier of the interprocessor interrupt; and invoke an interrupt handler for the interprocessor interrupt identified by the interrupt control data structure.