User-Space DMA Controller for Asynchronous Data Transfer
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Solution Overview
Problem
Existing data transfer methods between memory and external devices often burden the CPU, as they require direct intervention and cannot be controlled by user programs, leading to inefficient data transfer operations.
Innovation Solution
A data transfer apparatus and method that allows user programs to asynchronously request data transfers by specifying virtual addresses, with an acquisition unit, identification unit, and transcription unit to handle the transfer requests independently of CPU processing, enabling asynchronous data transfer between memory storage areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If DMA transfer is used for high-speed data transfer between memory and external devices, then data transfer speed is improved, but user program control is lost and CPU intervention is required
Solution Approach 1:
The patent introduces a user-space DMA controller that acts as an intermediary between user programs and the hardware DMA engine. This mediator enables user programs to issue DMA transfer requests directly without CPU intervention, while the hardware DMA engine handles the actual high-speed data transfer. The user-space controller translates user program commands into hardware-friendly DMA requests, resolving the contradiction between user control and high-speed transfer.
2Ease of operation
If CPU core performs data transfer in response to user program requests, then user program control is maintained, but CPU load increases
Solution Approach 1:
The patent extracts the data transfer function from the CPU core and places it in a dedicated user-space DMA controller. This separation allows user programs to maintain control over data transfers while the workload is handled by a specialized component rather than the general-purpose CPU. The CPU only needs to initiate transfers through the user-space controller, significantly reducing its load while preserving user program authority.
3Ease of operation
If DMA transfer is executed after CPU determines necessity and provides instruction, then CPU control is maintained, but transfer initiation delay increases
Solution Approach 1:
The patent implements preliminary action by allowing user programs to pre-configure DMA transfer requests in advance. The user-space DMA controller can prepare transfer parameters and buffer allocations before actual data transfer is needed. This enables faster transfer initiation by having the infrastructure ready, while the CPU maintains control through the user-space controller that manages when transfers are actually executed.
Data Source
AI summary
A processor includes a CPU core which executes a user program, and a data transfer apparatus. The CPU core stores a transfer request from a user program in a specific area of a main memory, in which the transfer request specifies the virtual addresses of a transfer source and a transfer destination in a memory space allocated to the user program. The data transfer apparatus refers to the specific area of the main memory and acquires a transfer request asynchronously to processing performed by the CPU core. The data transfer apparatus then identifies physical addresses corresponding to virtual addresses specified in the transfer request. After that, the data transfer apparatus transcribes original data stored in a storage area indicated by the physical address of the transfer source, to a storage area in a cache memory related to the virtual address or physical address of the transfer destination.