USR Chiplet Packaging for High-Throughput Inter-Die Links
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Solution Overview
Problem
Current semiconductor packaging technologies, such as silicon interposers and Intel's EMIB, face limitations in throughput and cost due to the use of micro bumps for die-to-die interconnects, which also degrade package yield and complicate timing closure and verification.
Innovation Solution
The implementation of ultra short reach (USR) chiplets with high density interconnects, including vertical connections and redistribution layer routes, to provide high throughput data transfer between main chips without modifying the main chip interfaces, using embedded silicon technology in organic substrates to reduce the number of traces and parasitic resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If micro bumps are used for die-to-die interconnects in silicon interposers and EMIB, then inter-die connectivity is achieved, but throughput is limited and cost increases
Solution Approach 1:
The patent segments the interconnect function by separating the high-speed SerDes interface (in the chiplet) from the inter-die transmission medium (substrate traces). This allows the chiplet to provide high-throughput capability while the substrate provides extended reach, resolving the throughput limitation of traditional micro bump interconnects.
Solution Approach 2:
The patent introduces an intermediary chiplet that acts as a bridge between the main chip and the substrate. The chiplet contains the SerDes interface and converts parallel data from the main chip into serial data for transmission over the substrate, enabling high throughput while using the substrate as a transmission medium rather than relying solely on micro bumps.
2Reliability
If silicon interposers are used for high-density interconnects, then inter-die connectivity is achieved, but cost increases
Solution Approach 1:
The patent extracts the SerDes interface functionality from the main chip and places it in a separate chiplet. This allows the main chip to use simpler, lower-cost substrate traces for inter-die connectivity rather than requiring expensive silicon interposer technology, while still achieving high throughput through the chiplet's SerDes capability.
Solution Approach 2:
The patent replaces expensive silicon interposer technology with a more cost-effective chiplet-based solution. The chiplet serves as an affordable intermediary that provides the necessary high-speed interface functionality without the high cost of silicon interposers, making high-throughput inter-die connectivity more economically viable.
3Productivity
If more traces are used in the substrate for data transfer, then throughput increases, but parasitic resistance increases and cost increases
Solution Approach 1:
The patent uses serial data transmission with periodic clocking through the SerDes interface. This allows high throughput to be achieved over fewer traces by transmitting data in sequential form rather than requiring numerous parallel traces, thereby reducing parasitic resistance while maintaining high productivity.
Data Source
AI summary
Systems and methods are provided for a system in a package (SiP) connectivity using one or more ultra short reach (USR) chiplets. The USR chiplet can receive/transmit data at a lower throughput and transmit/receive that data at a higher throughput over ultra short distances. The USR chiplet can be connected to a main integrated circuit (IC) using a high density interconnect or integrated with the main IC in a mold material. The USR chip can enable the main IC to transfer data over a substrate at a higher speed using a fewer number of traces.