3D UTB Transistor Using 2D Material Channels
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Solution Overview
Problem
Conventional semiconductor transistors have limitations in miniaturization and gate control efficiency due to their three-dimensional structure, which restricts their performance and footprint in electronic devices.
Innovation Solution
The use of three-dimensional structures with two-dimensional materials, such as graphene, transition metal dichalcogenides, and boron nitride, to form ultra-thin body transistors, allowing for increased gate width while maintaining a smaller footprint and improved gate control by forming 2D material layers in trenches and fins within dielectric layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional three-dimensional transistor structures are used, then manufacturing process is simpler, but gate control efficiency deteriorates and footprint is larger
Solution Approach 1:
The patent transitions from conventional three-dimensional bulk semiconductor structures to two-dimensional material channels (such as graphene, transition metal dichalcogenides, and boron nitride). This dimensional reduction enables ultra-thin body transistors that achieve superior gate control efficiency while maintaining a compact footprint, as the 2D material channels provide better electrostatic control and reduced short-channel effects compared to traditional 3D structures
2Productivity
If transistor size is reduced for miniaturization, then device density increases, but gate control efficiency deteriorates
Solution Approach 1:
The patent employs composite material structures combining 2D material channels with dielectric layers and gate electrodes. The ultra-thin body 2D material channels provide excellent electrostatic control that maintains gate control efficiency even as device dimensions are reduced for miniaturization, while the composite structure of 2D materials with dielectric and conductive layers enables high device density through improved scaling
Data Source
AI summary
A semiconductor device and a method of manufacture are provided. A substrate has a dielectric layer formed thereon. A three-dimensional feature, such as a trench or a fin, is formed in the dielectric layer. A two-dimensional layer, such as a layer (or multilayer) of graphene, transition metal dichalcogenides (TMDs), or boron nitride (BN), is formed over sidewalls of the feature. The two-dimensional layer may also extend along horizontal surfaces, such as along a bottom of the trench or along horizontal surfaces of the dielectric layer extending away from the three-dimensional feature. A gate dielectric layer is formed over the two-dimensional layer and a gate electrode is formed over the gate dielectric layer. Source/drain contacts are electrically coupled to the two-dimensional layer on opposing sides of the gate electrode.