UTBB FDSOI Current Source Array with Substrate Biasing
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Solution Overview
Problem
Conventional current source arrays in microelectronics are large, power-hungry, and complex, making them unsuitable for compact and efficient applications in circuits like digital to analog converters and filters.
Innovation Solution
A current source array utilizing a chain of Ultra Thin Body and Box Fully Depleted Silicon On Insulator (UTBB FDSOI) transistors with back gate biasing through the resistive path of the semiconductor well to achieve different threshold voltages and current values, reducing power consumption and complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If conventional current source arrays are used, then current source functionality is provided, but the area occupied is large
Solution Approach 1:
The patent merges multiple current source functions into a single array structure using UTBB FDSOI transistors with shared substrate biasing. Multiple transistors are arranged in an array where the substrate acts as a common biasing network, eliminating the need for separate biasing circuits for each current source, thus reducing area and complexity
Solution Approach 2:
The patent utilizes the substrate dimension as an additional control dimension for threshold voltage adjustment. By applying different bias voltages to different regions of the substrate, the invention creates a new degree of freedom for controlling transistor characteristics without adding external components, thereby reducing area
2Use of energy by moving object
If conventional current source arrays are used, then current source functionality is provided, but power consumption is high
Solution Approach 1:
The substrate serves multiple functions simultaneously: it acts as the mechanical support for the transistor array, the electrical isolation layer, and the biasing network for threshold voltage control. This multi-functionality eliminates the need for separate biasing circuits, reducing both power consumption and complexity
Solution Approach 2:
The UTBB FDSOI transistors utilize their own substrate as the biasing element, eliminating the need for external biasing circuits. The substrate automatically provides the necessary threshold voltage control through resistive paths, making the system self-sufficient and reducing overall power consumption
3Device complexity
If conventional current source arrays are used, then current source functionality is provided, but design complexity is high
Solution Approach 1:
The invention segments the substrate into multiple regions, each corresponding to a transistor in the array. Each region can be independently biased through resistive paths, allowing individual threshold voltage control without requiring separate external circuits for each transistor, thus simplifying design while maintaining area efficiency
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution results in a compact current source array with lower power consumption and complexity, enabling efficient operation in various microelectronic circuits.
Implementation Method 1
the biasing of a back gate (ground plane) through the resistive path of the underlying semiconductor well to provide the transistors with different threshold voltages
Implementation Method 2
applying the biasing voltage difference on the semiconductor well leads to apply a voltage just under the part of the insulating buried layer located below the transistors, this voltage being different from one transistor to another because of the intrinsic resistive path of the semiconductor well. This changes the electrostatic control of the transistors and shifts their threshold voltage
Data Source
AI summary
A Silicon On Insulator current source array includes input control for receiving a control voltage, a first reference input for receiving a first reference voltage, and a second reference input for receiving a second reference voltage. A chain of several Silicon On Insulator MOS transistors, of the same type, have control electrodes all connected to the input control, first conduction electrodes are all connected to the first reference input, and second conduction electrodes are respectively connected to the second reference input through several load circuits respectively configured to be traversed by several currents when the several transistors are ON upon application of the control voltage on the input control. An input bias is coupled to a semiconductor well located below an insulating buried layer located below the chain of transistors for receiving a biasing voltage difference.