UTBB FDSOI Transistor Gate Wrapping for Drain Current
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Solution Overview
Problem
As integrated circuit technology scales down, maintaining high current density while reducing transistor dimensions is challenging, particularly due to limitations in increasing channel width without compromising the number of transistors that can be formed in a given area, and the need to reduce supply voltages to minimize power consumption and prevent transistor damage.
Innovation Solution
The solution involves positioning the gate dielectric and gate electrode not only above the semiconductor substrate but also on the exposed sidewalls, thereby increasing the channel width by the thickness of the semiconductor substrate, allowing for a greater effective channel width that includes the top surface, sidewalls, and bottom surface exposure, which can increase the drain current without increasing the transistor area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the channel width is increased to increase drain current, then the current footprint is improved, but the number of transistors that can be formed in a given area decreases
Solution Approach 1:
The patent extends the gate dielectric and gate electrode from a planar configuration to a three-dimensional structure that wraps around the channel region. The gate electrode is positioned on the top surface, sidewalls, and bottom surface of the channel, effectively utilizing vertical and lateral dimensions to increase the channel width without increasing the planar footprint. This dimensional transition allows the channel to be accessed from multiple directions, achieving higher current density within the same area.
2Productivity
If the transistor dimensions are decreased to increase the number of transistors per area, then the integration density is improved, but the current density decreases
Solution Approach 1:
By transitioning from a two-dimensional planar channel to a three-dimensional channel structure with gate coverage on top, sidewalls, and bottom surfaces, the patent achieves higher current density in smaller transistors. This allows more transistors to be packed into a given area while each transistor maintains high current capability through its enhanced effective channel width.
3Use of energy by moving object
If the supply voltage is decreased to reduce power consumption, then the energy efficiency is improved, but the drain current decreases
Solution Approach 1:
The patent changes the geometric parameters of the transistor structure, specifically increasing the effective channel width by adding gate control on sidewalls and bottom surface. This structural parameter change compensates for the reduced supply voltage, allowing the transistor to maintain high drain current even at lower voltages, thus achieving both energy efficiency and high current output.
Data Source
AI summary
An integrated circuit die includes a substrate having a first layer of semiconductor material, a layer of dielectric material on the first layer of semiconductor material, and a second layer of semiconductor material on the layer of dielectric material. An extended channel region of a transistor is positioned in the second layer of semiconductor material, interacting with a top surface, side surfaces, and potentially portions of a bottom surface of the second layer of semiconductor material. A gate dielectric is positioned on a top surface and on the exposed side surface of the second layer of semiconductor material. A gate electrode is positioned on the top surface and the exposed side surface of the second layer of semiconductor material.