UTBB FDSOI Split Gate Devices for High Voltage Breakdown
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Solution Overview
Problem
Current fully depleted silicon-on-insulator (FDSOI) semiconductor devices lack high voltage capabilities for applications like power amplifiers and power management due to inadequate breakdown voltage, leading to issues such as punch-through, avalanche breakdown, and gate oxide breakdown as operating voltages increase.
Innovation Solution
Implementing a split gate topology with varying thickness gate dielectric layers and a split N/P well structure to enhance breakdown voltage while maintaining low turn-on voltage, achieved by using a thinner gate dielectric layer near the source and a thicker layer near the drain, and employing complementary doping in the N/P wells to control threshold voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a standard gate dielectric layer is used in FDSOI devices, then manufacturing is simple, but breakdown voltage is inadequate for high voltage applications
Solution Approach 1:
The gate dielectric layer is segmented into two distinct portions: a first gate dielectric layer portion and a second gate dielectric layer portion. This segmentation allows each portion to have different thickness characteristics, with the first portion providing thinner insulation for lower turn-on voltage and the second portion providing thicker insulation for higher breakdown voltage, thereby resolving the contradiction between simple manufacturing and adequate breakdown voltage.
Solution Approach 2:
Different regions of the gate dielectric structure are assigned different local qualities through varying thickness. The first gate dielectric layer portion has a thinner local thickness optimized for turn-on characteristics, while the second gate dielectric layer portion has a thicker local thickness optimized for breakdown voltage. This local quality differentiation enables the device to simultaneously achieve low turn-on voltage and high breakdown voltage.
2Power
If operating voltage is increased to achieve high voltage application performance, then power handling capability improves, but breakdown occurs causing uncontrollable current increase
Solution Approach 1:
The gate dielectric thickness parameter is changed across different regions of the device. By implementing a non-uniform thickness profile where the first gate dielectric layer portion is thinner and the second gate dielectric layer portion is thicker, the device can operate at higher voltages for improved power handling while the thicker second portion prevents breakdown by providing sufficient insulation barrier.
3Ease of operation
If gate dielectric layer is made thinner to reduce turn-on voltage, then switching performance improves, but breakdown voltage decreases
Solution Approach 1:
The gate dielectric is segmented into two functional portions with different thicknesses. The first gate dielectric layer portion is designed with thinner thickness to facilitate easy turn-on and low switching voltage, while the second gate dielectric layer portion is designed with thicker thickness to provide adequate breakdown voltage protection, thereby resolving the contradiction between ease of operation and reliability.
Solution Approach 2:
Different local thickness qualities are assigned to different gate dielectric portions. The first portion has local quality optimized for low turn-on voltage (thinner), while the second portion has local quality optimized for high breakdown voltage (thicker), enabling the device to simultaneously achieve ease of operation and reliability.
Data Source
AI summary
An Ultra Thin Body and Box (UTBB) fully depleted silicon on insulator (FDSOI) field effect transistor (FET) employing a split gate topology is provided. A gate dielectric layer is disposed beneath a gate structure and in contact with a channel layer of the device. The gate dielectric layer contains two portions, a thin portion and a thick portion. The thin portion is arranged and configured to reduce a trans-conductance of the device, while a thick portion is arranged and configured to increase the break down voltage of the device. The device further contains a bulk region that can be electrically connected to voltage source to provide control over the threshold voltage of the device.