Ultra Thin Channel MOSFET With Segmented Buried Oxide
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Solution Overview
Problem
Existing Ultra-Thin (UT) SOI MOSFET devices face issues with fringing electric fields, reduced speed due to thin BOX layers, inefficient stress transfer to the channel, and high gate-to-source/drain capacitance, which are exacerbated by the need for thick sidewall spacers and the introduction of oxygen ions that cause dislocations in silicon substrates.
Innovation Solution
The formation of a complex geometry Buried OXide (BOX) structure using porous silicon regions converted to silicon oxide, allowing for embedded thick source-drain regions that reduce series resistance and enable higher channel strain, along with the use of thinner gate sidewall spacers and a replacement gate process for improved device scaling and reduced leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a thin BOX layer is used in UTC SOI devices, then fringing is reduced, but device speed is reduced due to electric field fringing in the BOX
Solution Approach 1:
The BOX layer is segmented into two distinct layers: a first BOX layer extending across the channel and source/drain regions, and a second BOX layer extending only under the source/drain regions. This segmentation allows the first BOX layer to be thinner (reducing fringing) while the second BOX layer provides additional insulation (maintaining speed) by preventing electric field fringing from reaching the substrate.
2Object-generated harmful factors
If thick sidewall spacers are used to minimize gate to source-drain capacitance, then capacitance is reduced, but stress transfer to the channel is reduced
Solution Approach 1:
The invention moves the stress source from a lateral position (requiring thin spacers for stress transfer) to a vertical position by embedding source/drain regions deeper into the substrate. The second BOX layer enables this vertical embedding, allowing stress liners to be positioned closer to the channel in the vertical dimension while maintaining adequate lateral spacing for capacitance reduction.
3Object-generated harmful factors
If source-drain regions are elevated (Raised Source/Drain), then series resistance is reduced, but stress transfer efficiency is reduced due to increased distance from stress liners to channel
Solution Approach 1:
Instead of elevating source/drain regions laterally above the channel plane, the invention embeds them vertically deeper into the substrate by etching through the first BOX layer and forming source/drain regions in the substrate below. This vertical embedding maintains lateral alignment with the channel for efficient stress transfer while achieving low series resistance through increased conductive path length in the vertical dimension.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances performance by increasing channel strain, reducing extrinsic source-drain resistance, minimizing overlap capacitance, and allowing for closer placement of source-drain regions to the gate, thereby improving the overall performance of UT SOI MOSFET devices while suppressing short channel effects.
Implementation Method 1
Oxygen ion is implanted into a silicon substrate to remain a silicon layer on a surface of the silicon substrate. In this state, a silicon oxide layer is formed under the silicon layer. Silicon oxide particles are formed and remained in the residual silicon layer.
Implementation Method 2
The silicon oxide particles prevent the rise of dislocation to the surface of the SOI layer, and also suppress a rate per a unit time at which interstitial silicon generates during the heating to the high temperature region. Therefore, a dislocation density of the SOI layer can be reduced.
Implementation Method 3
The formation of a complex geometry Buried OXide (BOX) structure using porous silicon regions converted to silicon oxide
Data Source
AI summary
A MOSFET structure includes a planar semiconductor substrate, a gate dielectric and a gate. A UT SOI channel extends to a first depth below the top surface of the substrate and is self-aligned to and is laterally coextensive with the gate. Source-drain regions, extend to a second depth greater than the first depth below the top surface, and are self-aligned to the UT channel region. A BOX1 region extends across the entire structure, and vertically from the second depth to a third depth below the top surface. An upper portion of a BOX2 region under the UT channel region is self-aligned to and is laterally coextensive with the gate, and extends vertically from the first depth to a third depth below the top surface, and where the third depth is greater than the second depth.