UV-Opaque NVM Cell Structure for Data Retention Under UV Erase
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Solution Overview
Problem
Existing non-volatile memory (NVM) bitcells face challenges in data retention due to UV illumination processes, which can activate nitride charge traps and compromise data integrity, while reducing UV doses may not effectively erase accumulated charge and impact other IC components.
Innovation Solution
Incorporating UV-opaque structures around floating gate storage cells to modulate UV radiation dosage, creating a 'UV shadow' effect that balances charge erasure with data retention performance, optimizing UV dosage for different NVM products and process technologies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If UV illumination is applied to erase accumulated charge in floating gate storage cells, then charge erasure is achieved, but data retention performance is compromised due to activation of nitride charge traps
Solution Approach 1:
The patent applies different UV radiation doses to different regions of the semiconductor device. Specifically, floating gate storage cells receive a reduced UV dose (first UV dose) compared to other IC components (second UV dose), allowing selective protection of the floating gate cells from excessive UV exposure that activates nitride charge traps, while still enabling adequate charge erasure and maintaining overall device functionality
Solution Approach 2:
The UV illumination process is segmented into at least two separate illumination steps with different doses. The first UV illumination step applies a lower dose specifically targeted at floating gate storage cells to prevent charge trap activation, while subsequent steps apply higher doses to other components that require more aggressive UV treatment for charge erasure
2Reliability
If UV dose is reduced to protect data retention, then nitride trap formation is reduced, but accumulated charge erasure becomes ineffective
Solution Approach 1:
The UV illumination is applied in periodic, discrete steps rather than as a single continuous exposure. Multiple UV illumination steps are performed sequentially, with the first step using a reduced dose to protect data retention, and subsequent steps using higher doses to complete the charge erasure process, thereby achieving both data retention and effective charge removal
3Productivity
If high UV dose is applied to ensure charge erasure, then charge removal is effective, but other IC components are degraded
Solution Approach 1:
Different UV radiation doses are applied to different regions of the semiconductor device. Floating gate storage cells receive a reduced UV dose (first UV dose) to protect their data retention characteristics, while other IC components receive a higher UV dose (second UV dose) that is sufficient for effective charge erasure without compromising the floating gate cells
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The UV-opaque structures effectively manage UV radiation to ensure data retention and integrity by optimizing UV dosage, reducing nitride trap formation and maintaining the performance of NVM devices without degrading other IC components.
Implementation Method 1
UV-opaque structures associated with a floating gate (FG) storage cell for modulating the amount of UV radiation used in erasing accumulated charge
Data Source
AI summary
An integrated circuit comprises a transistor extending into a semiconductor substrate and having a gate structure having major and minor axes parallel to a surface of the semiconductor substrate, and a UV-opaque sheet structure vertically spaced apart from a top surface of the gate structure by a first distance and including an opening, the opening having first and second sides about parallel to the major axis, at least one of the first and second sides laterally spaced apart from a corresponding side of the gate structure by a second distance that is less than or equal to the first distance.


