UV-Resistant Floating Gate for Non-Volatile Memory Programming
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Solution Overview
Problem
Existing non-volatile memory integrated circuits require external circuits for programming after manufacturing, leading to increased chip size due to the need for additional pins for post-manufacturing programming.
Innovation Solution
The integration of ultraviolet-erasable non-volatile memory arrays that allow programming during the manufacturing process by using a UV-resistant material to prevent charge discharge from floating gates, enabling in-line programming and reducing the pin count, thus minimizing chip size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If external circuits are used for post-manufacturing programming, then programming functionality is achieved, but chip size increases due to additional pins
Solution Approach 1:
The patent applies preliminary action by programming the non-volatile memory during the manufacturing process before the chip is completed and packaged. The memory is programmed to desired states (e.g., all zeros or all ones) during fabrication, eliminating the need for post-manufacturing programming circuits and pins, thereby reducing chip size while maintaining programming functionality
Solution Approach 2:
The patent extracts the programming operation from the final product by completing it during manufacturing. By taking out the need for post-manufacturing programming interfaces and external circuits, the chip size is reduced while the programming capability is preserved through in-line manufacturing processes
2Productivity
If UV exposure is applied for programming, then memory states are programmed, but floating gate charge may discharge unintentionally
Solution Approach 1:
The patent introduces an intermediary UV-blocking layer between the UV source and the floating gate. This layer selectively blocks UV radiation from reaching specific memory cells, preventing unintentional charge discharge while allowing UV exposure to program other cells. The intermediary layer enables reliable charge retention during the UV programming process
Solution Approach 2:
The patent applies local quality by creating spatially selective UV exposure through the UV-blocking layer. Different regions of the memory array have different UV transmission properties, allowing specific cells to be programmed or erased while protecting other cells from UV exposure, thus maintaining charge retention where needed while enabling programming where required
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables reduced chip size by eliminating the need for post-manufacturing programming, with the UV-resistant material ensuring that floating gates remain charged after UV exposure, facilitating efficient in-line programming and testing.
Implementation Method 1
an ultraviolet-resistant or blocking material vertically disposed above the floating gate
Implementation Method 2
exposing the non-volatile array to a UV source
Data Source
AI summary
A method of forming a semiconductor memory storage device that includes forming first and second doped regions of a first type in a semiconductor substrate and laterally spaced from one another, forming a gate dielectric extends over the semiconductor substrate between the first and second doped regions, forming a floating gate on the gate dielectric, and forming an ultraviolet (UV) light blocking material vertically disposed above the floating gate such that the floating gate remains electrically charged after the semiconductor memory storage device is exposed to UV light.