UHV NMOS Device P-Top Layer Isolation
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Solution Overview
Problem
Current semiconductor technologies face challenges in achieving high breakdown voltage and effective isolation between ultra-high voltage (UHV) devices and adjacent low-voltage CMOS circuits, particularly in manufacturing high-voltage integrated circuits that require both actuation and data processing functions.
Innovation Solution
The development of an ultra-high voltage n-type-metal-oxide-semiconductor (UHV NMOS) device with a P-type substrate, high-voltage N-well regions, source and bulk p-wells, a P-Top layer, and an n-type implant layer, which improves performance by enhancing the I/V curve and providing self-shielding and isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional CMOS technologies are used for dual functions, then device integration is achieved, but breakdown voltage is insufficient for high-voltage applications
Solution Approach 1:
The device is segmented into distinct high-voltage and low-voltage regions with separate well structures (N-well for HV, P-well for LV). The N-well contains the high-voltage channel and drain, while the P-well contains the low-voltage source and bulk, allowing each region to be optimized for its specific voltage requirement
Solution Approach 2:
Different doping concentrations and well depths are applied locally to different regions. The N-well has a specific doping concentration optimized for high-voltage operation, while the P-well has different doping characteristics for low-voltage operation. The P-Top layer provides localized field control in the high-voltage region
2Adaptability or versatility
If high-voltage device structures are integrated with low-voltage device structures on a single chip, then functional integration is improved, but isolation between UHV device and adjacent CMOS circuit becomes challenging
Solution Approach 1:
The P-Top layer acts as an intermediary structure between the N-well (high-voltage region) and the P-well (low-voltage region). This intermediate layer provides field control and potential isolation, preventing direct interaction between the high-voltage and low-voltage regions while allowing both to coexist on the same chip
Solution Approach 2:
The substrate is segmented into spatially separated high-voltage and low-voltage regions with distinct well structures. The N-well region for high-voltage operation is physically separated from the P-well region for low-voltage operation, with the P-Top layer providing additional spatial separation and field control between the regions
3Length of moving object
If device dimensions are downscaled, then device size is reduced, but breakdown voltage performance deteriorates
Solution Approach 1:
The invention changes key parameters including well depth, doping concentration, and the introduction of the P-Top layer to maintain breakdown voltage performance in smaller devices. By adjusting these parameters, the device achieves high breakdown voltage without requiring large physical dimensions
Data Source
AI summary
An ultra-high voltage n-type-metal-oxide-semiconductor (UHV NMOS) device with improved performance and methods of manufacturing the same are provided. The UHV NMOS includes a substrate of P-type material; a first high-voltage N-well (HVNW) region disposed in a portion of the substrate; a source and bulk p-well (PW) adjacent to one side of the first HVNW region, and the source and bulk PW comprising a source and a bulk; a gate extended from the source and bulk PW to a portion of the first HVNW region, and a drain disposed within another portion of the first HVNW region that is opposite to the gate; a P-Top layer disposed within the first HVNW region, the P-Top layer positioned between the drain and the source and bulk PW; and an n-type implant layer formed on the P-Top layer.