Machine Learning Models for UVM Test Sequence Selection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current design verification methods for integrated circuits are time-consuming and prone to errors due to the manual generation of test sequences, often missing corner cases and requiring significant human intervention.
Innovation Solution
A system utilizing machine learning models to automatically generate and select test sequences by training on target states, integrating machine learning components within the universal verification methodology (UVM) environment to enhance sequence selection and verification efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If manual or random test sequence generation methods are used, then human control and flexibility are maintained, but verification time is excessive and corner cases are missed
Solution Approach 1:
The system enables self-service by allowing the design verification process to automatically generate and execute test sequences without continuous human intervention. The automated agent independently performs sequence generation, selection, and execution, reducing reliance on manual operations while improving verification completeness and efficiency
Solution Approach 2:
The patent replaces the manual mechanical process of test sequence generation with an automated intelligent agent that uses machine learning algorithms. This substitution transforms the verification process from human-controlled random generation to automated intelligent sequence selection, significantly reducing verification time while improving coverage of corner cases
2Reliability
If manual test sequence generation is used, then human expertise can be applied, but errors and omissions increase
Solution Approach 1:
The automated agent performs self-service by independently generating, selecting, and executing test sequences without requiring human intervention for each step. This reduces human errors and omissions while maintaining the complexity management through automated tracking and reporting mechanisms
3Reliability
If comprehensive test sequences are generated to cover all corner cases, then verification reliability improves, but the time and computational resources required increase significantly
Solution Approach 1:
The system implements feedback mechanisms where the automated agent learns from previous verification results and adjusts test sequence generation accordingly. This feedback loop enables the system to identify and focus on uncovered corner cases while avoiding redundant testing, thereby improving both coverage and efficiency simultaneously
Solution Approach 2:
The verification process is made dynamic through the automated agent that adapts test sequence generation based on real-time feedback from design verification results. The system dynamically adjusts the testing strategy to prioritize unexplored corner cases, optimizing the balance between comprehensive coverage and verification efficiency
Data Source
AI summary
An approach is disclosed herein to sequence selection in a UVM environment. Generally, this approach includes a training phase for each machine learning model of a plurality of machine learning models. Each model is trained to achieve a particular target state and is rewarded when a selected action or sequence of actions causes movement that might be beneficial to achieving that target state. Once a respective model is trained, the trained model can then be used to determine which one action or sequence of actions (or ordered multiple thereof) to take to achieve the corresponding target state. Thus, by training and using a plurality of machine learning models to achieve a plurality of target states, and stimulating those machine learning models once trained, one or more actions and/or sequences of actions are generated as the selected sequences to be used to verify functionality or operation of a design under test.