UWB Clock Synthesizer Using One PLL for Multi-Frequency Generation
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Solution Overview
Problem
UWB transceivers require multiple phase-locked loops (PLLs) that consume significant power and occupy large circuit area, increasing power consumption and product costs.
Innovation Solution
Implement a clock signal synthesizer that generates multiple clock signals using a single oscillator and frequency dividers, reducing the number of PLLs to three or fewer, thereby generating clock signals efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple phase-locked loops (PLLs) are used to generate clock signals, then reliable clock signal generation is achieved, but power consumption and circuit area increase significantly
Solution Approach 1:
The patent merges multiple PLL functions into a single PLL by using frequency dividers with different division ratios to generate multiple clock signals (e.g., 40 MHz, 80 MHz, 160 MHz) from one phase-locked loop, thereby reducing the total number of PLLs from multiple to one and significantly lowering power consumption
Solution Approach 2:
A single PLL is designed to serve multiple functions by generating various clock frequencies required by different blocks (baseband transmitter, DAC, upconverter) through programmable frequency dividers, making the PLL a universal clock source for the entire UWB transceiver
2Reliability
If multiple phase-locked loops (PLLs) are used to generate clock signals, then reliable clock signal generation is achieved, but circuit area increases significantly
Solution Approach 1:
The patent merges multiple PLL circuits into a single PLL implementation, using frequency division techniques to provide multiple clock frequencies, thereby reducing the circuit area occupied by clock generation components from multiple PLLs to one PLL plus divider circuits
Solution Approach 2:
The patent implements a nested structure where frequency dividers are integrated within or closely coupled to the PLL circuit, allowing multiple clock signals to be generated through nested frequency division stages (e.g., dividing by 2, 4, 8) from the main PLL output, optimizing space utilization
3Use of energy by stationary object
If the number of PLLs is reduced to three or fewer, then power consumption and circuit area are minimized, but clock signal generation complexity increases
Solution Approach 1:
The patent introduces frequency dividers as intermediary components between the single PLL and the various clock-consuming blocks, allowing the PLL to generate a master clock signal that is then divided into multiple frequencies, thereby managing complexity through modular intermediate stages rather than direct complex PLL design
Data Source
AI summary
An apparatus, including: an oscillator configured to generate a clock signal; a clock signal synthesizer configured to generate a first clock signal, a second clock signal, and a third clock signal, wherein the first, second, and third clock signals are based on the clock signal; a baseband transmitter configured to generate a transmit baseband digital signal in response to the first clock signal; an ultra-wideband (UWB) pulse digital-to-analog converter (DAC) configured to generate a UWB pulse signal based on the transmit baseband digital signal in response to the second clock signal; and a frequency upconverter configured to frequency upconvert the UWB pulse signal to generate a transmit radio frequency (RF) signal based on the third clock signal.