UWB Transceiver Sleep Timing Using PLL Clock Counters
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Solution Overview
Problem
Ultra-wideband wireless communication systems face challenges in achieving low power consumption and efficient power management, particularly in deep sleep modes, due to the lack of precise wake-up timing and high power consumption in existing transmitters and receivers.
Innovation Solution
The implementation of a method involving a PLL clock counter to track the number of PLL clock cycles between sleep signal activation and DC-DC converter shutdown, allowing for accurate wake-up timing, combined with the use of compounded MOSFET structures and biasless differential transconductance stages to reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the DC-DC converter is turned off during deep sleep mode to reduce power consumption, then power consumption is reduced, but wake-up timing precision deteriorates
Solution Approach 1:
The system segments the timing function by using two separate counters: a first counter that continues operating in deep sleep mode to maintain timing precision, and a second counter that operates when the DC-DC converter is active. This segmentation allows the timing function to be maintained without requiring the entire DC-DC converter system to remain powered on.
Solution Approach 2:
The first counter performs preliminary timing measurements during the transition to and from deep sleep mode, storing timing information that can be used when the DC-DC converter is off. This preliminary action ensures that timing precision is maintained even when the main power conversion system is dormant.
2Duration of action of moving object
If deep sleep mode is used to extend battery life, then duration of action is improved, but wake-up response time worsens
Solution Approach 1:
The first counter continuously tracks timing information even during deep sleep mode transitions, performing preliminary measurements that eliminate wake-up delays. By maintaining timing state information in advance, the system can transition from deep sleep to active state without losing time, thus extending battery life without sacrificing response time.
Solution Approach 2:
The system uses feedback from the first counter's timing measurements to adjust and optimize the wake-up timing, ensuring that the transition from deep sleep mode occurs at the precise moment needed. This feedback mechanism allows the system to maintain both long battery life and fast wake-up response.
3Use of energy by moving object
If low frequency clock sources are used in deep sleep mode, then power consumption is reduced, but timing precision deteriorates
Solution Approach 1:
The timing function is segmented between two counters operating at different clock frequencies. The first counter operates at high frequency for precision timing measurements, while the second counter operates at low frequency during deep sleep mode. This segmentation allows the system to achieve both low power consumption and high timing precision by using each counter in its optimal operating mode.
Solution Approach 2:
The system changes the operating parameters of the counters based on the power mode. During deep sleep mode, the first counter operates with high frequency for precision, while the second counter handles low frequency timing. This parameter change allows the system to maintain timing precision without requiring the entire system to consume high power continuously.
Data Source
AI summary
Ultra-Wideband (UWB) wireless technology transmits digital data as modulated coded impulses over a very wide frequency spectrum with very low power over a short distance. To support extended operation, particularly with battery power sources, the inventors have established UWB devices which support wake-up from deep sleep modes when these devices exploit low frequency clock sources for ultra-low power consumption. Further, power consumption may be reduced by exploiting transistors or so-called compounded MOSFET structures whose effective gain and output resistance exceeds any single transistor irrespective of length or by employing biasless low power differential (exponential) transconductance stages within operational transconductance amplifiers in order to provide very high gain low power amplification stages. Further, the inventors have established voltage reference sources that consume very low current, a few nA, and ultra-low power low dropout regulators.