V-Grooved Vertical Channel Memory Device
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Solution Overview
Problem
Existing three-dimensional non-volatile memory devices, such as vertical NAND strings, face challenges with high control gate/word line resistances and capacitances, which reduce cell efficiency and increase power consumption, and current connection methods are complex and costly, compromising memory density and read-out speed.
Innovation Solution
A method involving a stack of alternating conductive and dielectric materials with V-shaped trenches, where the channel liner connects memory strings in series without the need for slits or metal plugs, allowing for easier process control and higher density by using a filler material to separate cells within the trench.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal plugs are used to connect cells at the bottom like in Samsung V-NAND configuration, then electrical connection is achieved, but manufacturing complexity increases due to high aspect ratio etch and deposition requirements
Solution Approach 1:
The patent extracts the complex metal plug formation process and replaces it with a simpler trench isolation approach. By removing the need for metal plugs and high aspect ratio etching, the manufacturing process becomes less complex while maintaining electrical connection reliability through alternative means.
Solution Approach 2:
The patent introduces a trench structure filled with dielectric material as an intermediary element. This trench acts as a mediator that provides mechanical support and electrical isolation between adjacent memory strings, replacing the need for complex metal plug connections at the bottom of the stack.
2Area of stationary object
If a horizontal pipeline is constructed to connect adjacent strings at their bottom, then area consumption is reduced, but manufacturing complexity increases due to conformal layer requirements and slit needs
Solution Approach 1:
Instead of creating a horizontal pipeline at the bottom of the stack, the patent inverts the approach by using vertical trench structures that extend through the stack. This inversion eliminates the need for conformal layer deposition along horizontal tunnels and removes the requirement for slits between cell planes.
Solution Approach 2:
The patent transitions from a horizontal connection approach (pipeline) to a vertical connection approach (trenches extending through the stack). This dimensional change from horizontal to vertical allows for simpler manufacturing processes while achieving the same area efficiency goals.
3Ease of manufacture
If diffused regions are used to connect cells at the bottom like in NOR Flash, then manufacturing is simpler, but series resistance increases significantly
Solution Approach 1:
The patent uses a disposable trench structure filled with dielectric material that provides electrical isolation without requiring low-resistance conductive paths like diffused regions. This approach accepts the simplicity of the manufacturing process while managing resistance through alternative structural means rather than through highly conductive materials.
Data Source
AI summary
A method of fabricating a vertical channel 3D semiconductor memory device is disclosed. In one aspect, the method comprises providing a stack of alternating layers of conductive material and dielectric material on a major surface of substrate, providing in the stack at least one trench, having sloped sidewalls sloping towards the major surface, extending at least below the lowest layer of conductive material, forming, in order, a programmable material, a channel liner, and a filler material on the sidewalls of the trench. Thereby, the method forms a memory string, and an electrode to the channel liner at opposite ends of the memory string.