Vertical Nanowire FET Capacitance Cell Layout
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Solution Overview
Problem
Current semiconductor integrated circuits face challenges in securing sufficient capacitance values due to the increase in off-current and power consumption with excessive scaling, and noise-induced malfunctions become prevalent with higher operating frequencies and lower operating voltages, for which no effective solution using vertical nanowire FETs (VNW FETs) has been established.
Innovation Solution
A layout structure for a capacitance cell utilizing VNW FETs is designed, where first and second power supply interconnects are configured with VNW FETs, ensuring that at least one VNW FET has its top and bottom connected to the first power supply and its gate connected to the second power supply, forming decoupling capacitance through a gate oxide film, thereby securing a sufficient capacitance value.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional planar transistors are scaled down to improve integration degree and operating speed, then manufacturing precision and operating frequency are improved, but off current increases and power consumption increases significantly
Solution Approach 1:
The patent transitions from conventional planar transistors to three-dimensional vertical nanowire FETs. This dimensional change allows the channel to extend vertically through the substrate, achieving better gate control and reduced off-current while maintaining small footprint for high integration. The vertical architecture enables superior electrostatic control that suppresses short-channel effects and reduces leakage current.
2Loss of energy
If operating voltage is reduced to improve power consumption, then energy efficiency is improved, but noise immunity decreases and noise-induced malfunctions increase
Solution Approach 1:
The patent introduces decoupling capacitance cells formed by vertical nanowire FETs with specific gate-length-to-width ratios (L/W ≥ 0.5) to maintain noise immunity at lower operating voltages. These capacitance cells provide local charge storage that stabilizes power supply voltage and filters noise, enabling reliable operation at reduced voltages while maintaining noise immunity.
3Reliability
If decoupling capacitance is added to prevent noise-induced malfunctions, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent designs vertical nanowire FETs that can serve dual functions: as active switching transistors in logic circuits or as decoupling capacitance elements when configured with appropriate dimensions (L/W ≥ 0.5). This multi-functionality allows the same transistor technology to provide both logic functionality and power supply stabilization, reducing the need for separate dedicated capacitance structures and simplifying overall device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed layout structure effectively secures a capacitance value for VNW FETs, improving the performance of semiconductor integrated circuits by reducing noise-induced malfunctions and power consumption while maintaining high integration and operating speed.
Implementation Method 1
forming decoupling capacitance through a gate oxide film
Data Source
AI summary
A layout structure of a capacitance cell using vertical nanowire (VNW) FETs is provided. The capacitance cell includes a plurality of first-conductivity type VNW FETs lining up in the X direction, provided between a first power supply interconnect and a second power supply interconnect. The plurality of first-conductivity type VNW FETs include at least one first VNW FET having a top and a bottom connected with the first power supply interconnect and a gate connected with the second power supply interconnect.