V-Shaped Buffer Layer for Uniform InGaAs Channel Formation
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Solution Overview
Problem
The fabrication of high aspect ratio FinFETs with III-V materials on silicon substrates faces challenges such as lattice mismatch, valence difference, thermal property differences, conductivity differences, and anti-phase defects, leading to non-uniform channel thickness and decreased device yield as device sizes shrink.
Innovation Solution
A method involving the deposition of a dielectric material, etching to form a trench, filling with silicon, overfilling with a buffer material, planarizing, and etching into a v-shape, followed by depositing a channel material on a v-shaped buffer layer to achieve uniform InGaAs channel formation, mitigating facet formation and ensuring uniform indium and gallium distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If buffer material is deposited to reduce lattice mismatch and anti-phase defects, then defect reduction is achieved, but channel thickness uniformity deteriorates due to trench depth and critical dimension variation
Solution Approach 1:
Instead of depositing buffer material directly into the trench and hoping for uniform thickness, the patent inverts the approach by first forming a sacrificial silicon layer, etching it into a V-shape, and then depositing the buffer material. This inversion allows the buffer to conform to the V-shaped profile, ensuring uniform thickness despite variations in trench depth and critical dimensions.
Solution Approach 2:
The patent introduces a dimensional transformation by converting the trench from a rectangular cross-section to a V-shaped cross-section through selective etching of the silicon layer. This dimensional change in the buffer layer's base profile compensates for variations in trench depth and width, enabling uniform buffer thickness deposition across the wafer.
2Volume of moving object
If device dimensions are reduced to increase density, then device miniaturization is achieved, but channel uniformity and device yield deteriorate
Solution Approach 1:
For miniaturized devices, the patent inverts the conventional deposition approach by using a V-shaped sacrificial silicon layer as a template. This inversion ensures that even as device dimensions shrink, the buffer material conforms precisely to the V-shaped profile, maintaining uniform thickness and preventing defects that would otherwise worsen with smaller dimensions.
Solution Approach 2:
The patent changes the geometric parameters of the buffer layer's base structure from rectangular to V-shaped, and adjusts the etch selectivity between silicon and buffer materials. These parameter changes enable precise control of buffer thickness uniformity even in sub-5nm node devices, compensating for the increased sensitivity to dimensional variations at smaller scales.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of precise, uniform channel layers in sub-5 nm node FinFETS, reducing defects and improving device yield by ensuring uniform channel material distribution and counteracting facet growth.
Implementation Method 1
depositing a dielectric material on a substrate
Implementation Method 2
depositing a dielectric material on a substrate
Implementation Method 3
depositing a silicon material into the trench
Implementation Method 4
depositing a silicon material into the trench
Implementation Method 5
overfilling the trench with a buffer material
Implementation Method 6
overfilling the trench with a buffer material
Implementation Method 7
depositing a channel material in the v-shaped trench
Implementation Method 8
depositing a channel material in the v-shaped trench
Data Source
AI summary
Embodiments described herein generally provide a method and apparatus to form semiconductor devices. Specifically, embodiments describe an apparatus and methods of forming channels in sub-5 nm node FinFETS. The method provides for various processing steps to deposit a dielectric layer over a substrate. The method continues by etching a trench in the dielectric layer, depositing a silicon layer within the trench, depositing a buffer layer on top of the silicon layer in the trench, removing a portion of the buffer layer to form a planar surface, etching the buffer layer into a v-shape, and depositing a channel layer on top of the v-shaped buffer layer. The v-shaped buffer layer advantageously negates facet formation and provides for an InGaAs fin-channel with uniform distribution of indium and gallium throughout the channel.