V-Shaped DRAM Active Areas Reduce Leakage Current
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Solution Overview
Problem
The challenge in developing high-density dynamic random access memory (DRAM) arrays lies in scaling down memory cells without compromising memory capacity per unit area, and existing DRAMs face issues with leakage current due to word line interference, which degrades performance as feature sizes shrink.
Innovation Solution
A semiconductor layout structure for DRAM arrays featuring 'V'-shaped active areas with intersecting word lines, where the active areas are defined by an isolation structure and arranged in columns, with the 'V' shapes oriented in specific directions to terminate the migration path of free electrons during row hammer events, reducing leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell feature size is scaled down to increase circuit density, then memory capacity per unit area is improved, but leakage current due to word line interference increases
Solution Approach 1:
The active area is designed with an asymmetric 'V' shape instead of a conventional rectangular shape. The opening of the 'V' shape is oriented at a specific angle (140° to 170°) to asymmetrically block the migration path of free electrons caused by row hammer events, thereby reducing leakage current while maintaining high memory density
Solution Approach 2:
The solution addresses the two-dimensional word line interference problem by introducing a geometric dimensionality change - transforming the active area from a rectangular 2D shape to a 'V' shaped configuration. This dimensional transformation creates a physical barrier that disrupts the electron migration path in the horizontal dimension while maintaining vertical stacking for high density
2Productivity
If feature size of IC components is reduced to increase circuit density, then IC complexity and performance are improved, but process limits are approached and interference between word lines increases
Solution Approach 1:
The 'V' shaped active area introduces asymmetry to the conventional symmetric rectangular layout. This asymmetric geometry strategically positions the active region to minimize overlap and interference between adjacent word lines, allowing higher circuit density without proportionally increasing word line interference
Solution Approach 2:
The 'V' shape configuration provides local quality optimization by creating a specific geometric configuration in the active area that locally reduces electric field coupling between word lines. The opening angle and orientation are optimized to locally minimize interference in critical regions while maintaining overall high density
Data Source
AI summary
A semiconductor layout structure for a dynamic random access memory (DRAM) array comprises a plurality of active areas, an isolation structure and a plurality of word lines in a semiconductor substrate, where the isolation structure is situated among the plurality of active areas. Each of the plurality of active areas comprises a first segment extending in a first direction and a second segment extending in a second direction, one end of the first segment connected to an end of the second segment such that the active area presents a “V” shape. Two of the plurality of word lines intersect and traverse the first and second segments in each of the active areas respectively.