V-Shaped Epitaxial Source-Drain Valleys for Low Resistance
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Solution Overview
Problem
The challenge in the semiconductor industry is scaling down planar devices such as conventional MOSFETs, which results in limited area for connecting transistors, leading to increased junction resistance and degraded switching speed due to the small area available for transistor connections.
Innovation Solution
A semiconductor structure is developed with a v-shaped valley on the top surface of source and drain features, increasing the contact area with metal silicide layers and reducing contact resistance, achieved by forming recesses in the substrate and epitaxially growing semiconductor material within these recesses, followed by chemical vapor etching to create the v-shaped valley.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If planar devices are scaled down to increase device density, then functional density increases, but the area available for connecting transistors decreases, leading to increased junction resistance
Solution Approach 1:
The patent transitions from a conventional planar surface to a three-dimensional V-shaped valley structure. By etching recesses into the substrate and filling them with epitaxially grown semiconductor material, the invention creates vertical depth in addition to horizontal area, effectively increasing the contact area available for metal silicide layers without increasing the planar footprint. This dimensional change allows more connection area within the same chip area, thus reducing junction resistance while maintaining high device density.
Solution Approach 2:
The V-shaped valley structure nests additional contact area within the existing device footprint. The recesses are formed within the source/drain regions, and the epitaxial material fills these recesses to create extended contact surfaces. This nesting approach allows the contact area to be embedded within the device structure itself, providing increased junction area without occupying additional chip space, thereby resolving the contradiction between high density and low resistance.
2Reliability
If the contact area is increased to reduce junction resistance, then the switching speed improves, but the device geometry becomes more complex
Solution Approach 1:
The contact structure is segmented into multiple regions: the original planar contact area, the V-shaped valley recesses, and the epitaxially grown semiconductor material filling the recesses. This segmentation allows each portion to serve a specific function - the planar area provides primary contact, while the V-shaped valleys provide additional contact area for metal silicide layers. The segmentation enables increased total contact area without requiring a complete redesign of the entire device geometry, thus improving switching speed while managing complexity through functional division.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The increased contact area reduces contact resistance, enhancing the performance and power efficiency of the semiconductor structure by providing a greater interface for silicide layers and conductive contacts.
Implementation Method 1
epitaxially grown source and drain (S/D) features
Implementation Method 2
chemical vapor etching to create the v-shaped valley
Data Source
AI summary
The present disclosure provides a method in accordance with some embodiments. The method includes forming a recess in a source/drain region of a semiconductor substrate, wherein the semiconductor substrate is formed of a first semiconductor material. The method further includes epitaxially growing a second semiconductor material within the recess to form a S/D feature in the recess, and removing a portion of the S/D feature to form a v-shaped valley extending into the S/D feature.