V-Shaped Erase Gate for Low-Voltage MTP Memory
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Solution Overview
Problem
Current multiple-time programmable (MTP) non-volatile memory (NVM) devices require more masking operations and have larger memory cell sizes, making them less efficient compared to high-density NVMs like flash memories, and there is a need for improved erasure and programming methods that reduce voltage requirements and layout dependencies.
Innovation Solution
The design incorporates a memory device with a v-shaped erase gate and coupling gate, where the v-shaped portion of the second plate of the first capacitor extends into a recessed region of the workpiece, allowing for efficient erasure using Fowler-Nordheim tunneling at lower voltages and programming through channel hot electron injection, with self-aligned features that reduce the need for additional lithography masks and processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional MTP NVM structures are used, then memory functionality is achieved, but more masking operations are required and memory cell size increases
Solution Approach 1:
The patent merges the erase gate and coupling gate into a single integrated gate structure, eliminating the need for separate masking operations for each gate. This consolidation reduces the total number of lithography masks required while maintaining the functional independence of both gates through selective voltage application regions.
Solution Approach 2:
The single gate structure serves multiple functions: it acts as both an erase gate and a coupling gate depending on the voltage applied to different regions. This multi-functionality allows the same physical structure to perform multiple memory operations without requiring additional dedicated structures, thereby reducing both masking operations and cell size.
2Reliability
If conventional erasure methods are used, then data erasure is achieved, but high voltage requirements and over-erase issues occur
Solution Approach 1:
The gate structure implements local quality by having different regions of the gate serve different functions with different voltage requirements. The erase gate region can be controlled independently from the coupling gate region, allowing localized electric field generation for Fowler-Nordheim tunneling without requiring high voltages across the entire gate structure. This prevents over-erase by confining the high electric field to only the necessary region.
Solution Approach 2:
The integrated gate structure acts as an intermediary that mediates between the control electrodes and the charge storage node. By distributing the voltage application across different regions of the same gate structure, it enables controlled erasure through Fowler-Nordheim tunneling while preventing excessive voltage that would cause over-erase damage.
3Manufacturing precision
If additional lithography masks are added to improve alignment, then manufacturing precision increases, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent combines multiple gate functions into a single lithographically defined structure, eliminating the need for additional masking steps that would be required if separate erase and coupling gates were fabricated independently. This merging maintains alignment accuracy while reducing the total mask count.
Solution Approach 2:
The single gate structure is self-aligned by default since it is formed in a single lithography step. The internal region divisions between erase and coupling gate functions are defined by subsequent deposition and patterning steps that use the gate structure itself as a reference, eliminating the need for additional alignment-critical lithography masks.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enables MTP NVM devices to be erased and programmed at relatively low voltage levels, reduces the risk of over-erase issues, and improves data retention with less substrate current, while being easily integratable into existing manufacturing flows without requiring additional lithography masks or processes.
Implementation Method 1
allowing for efficient erasure using Fowler-Nordheim tunneling at lower voltages
Implementation Method 2
programming through channel hot electron injection
Data Source
AI summary
Representative methods of manufacturing memory devices include forming a transistor with a gate disposed over a workpiece, and forming an erase gate with a tip portion extending towards the workpiece. The transistor includes a source region and a drain region disposed in the workpiece proximate the gate. The erase gate is coupled to the gate of the transistor.