V-Shaped Epitaxial Layer for FinFET Current Distribution

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Solution Overview

Problem

Epitaxial layers in non-planar metal-oxide semiconductor transistors, such as fin field effect transistors (FinFETs), face challenges in achieving an even distribution of electrical current, affecting device performance.

Innovation Solution

A method is developed to fabricate a semiconductor device with a fin-shaped structure and an epitaxial layer having a V-shaped profile, which is formed adjacent to the gate structure using selective epitaxial growth, allowing the epitaxial layer to extend inward along the edge of the fin-shaped structure and shrink backward relative to the central region, thereby adapting to different electrical current densities.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If selective epitaxial growth technique is used to form epitaxial structure in silicon substrate, then carrier mobility is increased and speed of MOS transistor is improved, but the epitaxial layers cannot achieve even distribution of electrical current under different conditions

Engineering Contradiction:
Improvedevice performanceVSAvoidcurrent distribution uniformity
Core Design Contradiction:
ReliabilityVSEase of operation

Solution Approach 1:

The patent applies local quality by creating a V-shaped epitaxial layer with non-uniform thickness distribution. The epitaxial layer is thinner at the center and thicker at the edges, allowing different regions to serve different functions: the thinner central region provides less stress during on-state to maintain current uniformity, while the thicker edge regions provide sufficient stress for carrier mobility enhancement. This local variation in thickness resolves the contradiction between achieving even current distribution and maintaining device performance.

Inventive Principle:
Principle #3Local quality

2Speed

If epitaxial layer is formed to apply stress to gate channel, then carrier mobility is increased, but excessive stress is applied during off-state causing uneven current distribution

Engineering Contradiction:
Improvetransistor speedVSAvoidcurrent distribution uniformity
Core Design Contradiction:
SpeedVSEase of operation

Solution Approach 1:

The V-shaped epitaxial layer structure enables dynamic stress adaptation. During on-state, the thinner central region of the V-shaped layer provides reduced stress that prevents excessive current concentration, while during off-state, the overall layer structure maintains sufficient stress for carrier mobility. The shape allows the stress profile to dynamically adapt to different operational conditions, resolving the contradiction between speed enhancement and current distribution uniformity.

Inventive Principle:
Principle #15Dynamics

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach improves the distribution of electrical current, applying optimal stress during the on-state while preventing excessive stress during the off-state, enhancing the overall performance of the FinFET device.

Implementation Method 1

selective epitaxial growth (SEG) technique to form epitaxial structure such as silicon germanium (SiGe) epitaxial layer in a silicon substrate

Methodology Applied
Scientific EffectSelective epitaxial growth: Epitaxy

Implementation Method 2

As the lattice constant of the SiGe epitaxial layer is greater than the lattice constant of the silicon substrate thereby producing stress to the channel region

Methodology Applied
Scientific EffectLattice mismatch stress: Stress Relaxation

Implementation Method 3

silicon carbide (SiC) epitaxial layer could be formed in silicon substrate to produce tensile stress for gate channel of NMOS transistor

Methodology Applied
Scientific EffectLattice mismatch stress: Stress Relaxation

Data Source

PatentUS9640661B1FinFET having a fin and a V-shaped epitaxial layer formed on the top surface of the fin and method for fabricating the same
Publication Date: 2017.05.02 UNITED MICROELECTRONICS CORP
  • US9640661B1 patent drawing
  • US9640661B1 patent drawing
  • US9640661B1 patent drawing

AI summary

A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a fin-shaped structure is formed on the substrate. Next, a gate structure is formed on the fin-shaped structure, and an epitaxial layer is formed adjacent to the gate structure. Preferably, the epitaxial layer includes a V-shaped profile viewing from the top. According to the preferred embodiment of the present invention, the V-shaped profile of the epitaxial layer allows more stress to be applied to the region having concentrated currents or edges of the fin-shaped structures during an on-state, and at the same time prevent exerting too much stress to the region having high currents or central region of the fin-shaped structure during an off-state.