Voltage-to-Delay Preamplifier Array Gain Calibration for High-Speed ADCs

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing analog-to-digital converters face challenges in achieving high-speed operation with reduced area and power requirements, while also addressing gain mismatch and saturation issues across preamplifier arrays.

Innovation Solution

The proposed analog-to-digital converter system employs a voltage-to-delay preamplifier array with a folding delay multiplexer and a delay-resolving backend, which includes a calibration engine for gain normalization and saturation detection across the preamplifier array.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If conventional pipeline-based ADC architecture is used, then conversion accuracy can be maintained, but operating speed is limited and power consumption increases

Engineering Contradiction:
Improveoperating speedVSAvoidpower consumption
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

The patent replaces the conventional pipeline-based ADC architecture with a voltage-to-delay (V2D) based ADC architecture. This substitution fundamentally changes the conversion mechanism from voltage comparison stages to delay measurement, enabling high-speed operation (>3 GSPS) with reduced power consumption while maintaining conversion accuracy through the delay-resolving backend and calibration engine

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Measurement precision

If preamplifier array operates at high gain, then conversion accuracy improves, but gain mismatch and saturation issues arise

Engineering Contradiction:
Improveconversion accuracyVSAvoidgain matching accuracy
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The patent implements a calibration engine that performs gain normalization and saturation detection before the main conversion process. By pre-calibrating the preamplifier array gains and detecting saturation conditions in advance, the system ensures accurate gain matching and prevents saturation during high-gain operation, thereby maintaining both conversion accuracy and reliability

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The calibration engine continuously monitors preamplifier output levels and adjusts gains through feedback control. This feedback mechanism detects saturation conditions and compensates for gain mismatch dynamically, ensuring that the preamplifier array operates at optimal gain levels without saturation while maintaining conversion accuracy

Inventive Principle:
Principle #23Feedback

3Productivity

If delay-based ADC architecture is implemented, then high-speed operation with reduced area and power is achieved, but gain mismatch across preamplifier array must be corrected

Engineering Contradiction:
Improveoperating speedVSAvoidgain normalization complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The calibration engine serves multiple functions simultaneously: it performs gain normalization across the preamplifier array, detects saturation conditions, and stores calibration data for use during conversion. This multi-functional approach simplifies the overall system by consolidating calibration and monitoring tasks into a single integrated block, reducing the complexity that would otherwise arise from separate gain correction circuits

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentEP4268373B1Gain mismatch correction for voltage-to-delay preamplifier array
Publication Date: 2025.05.14 TEXAS INSTRUMENTS INC
  • EP4268373B1 patent drawingFigure 1
  • EP4268373B1 patent drawingFigure 2
  • EP4268373B1 patent drawingFigure 3

AI summary

A method of using an analog-to-digital converter system includes receiving a sampled voltage corresponding to one of an input voltage and a known voltage, causing preamplifiers to generate output signals based on the sampled voltage, generating first and second signals based on the output signals, causing a delay-resolving delay-to-digital backend to generate a single-bit digital signal representing an order of receipt of the first and second signals, and adjusting one or more of the preamplifiers based on the digital signal. The disclosure also relates to a system which includes a voltage-to-delay frontend and a delay-resolving backend, and to a method which includes causing a delay comparator to generate a single-bit digital signal representing an order of receipt of input signals, causing the comparator to transmit a residue delay signal to a succeeding comparator, and transmitting a signal to adjust one or more of the preamplifiers based on the digital signal.