V2X Message Verification Dispatch for Hardware Bottlenecks

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Solution Overview

Problem

The verification process for messages in vehicle-to-everything (V2X) systems is compute-intensive, leading to bottlenecks that slow down message transmission and reduce the efficiency of communication networks.

Innovation Solution

Implementing a smart dispatcher that distributes messages between verification logic software and hardware based on criteria such as load, priority, and type, allowing the processor to expand the verification capacity beyond the hardware limits, thereby reducing latency and costs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If verification logic is offloaded to dedicated hardware, then verification reliability is improved, but device complexity and transmission speed deteriorate

Engineering Contradiction:
Improvemessage verification reliabilityVSAvoidsystem complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The processor is designed to perform multiple functions: it can execute verification logic software for standard messages and switch to hardware verification for high-priority or time-critical messages. This multi-functionality allows the system to maintain reliability while avoiding the need for dedicated hardware for all verification operations, thus reducing overall system complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The system dynamically selects between software-based and hardware-based verification based on message characteristics, system load, and priority levels. This dynamic adaptation allows the system to optimize between reliability and complexity in real-time, using hardware only when necessary rather than maintaining permanent dedicated hardware for all verification tasks.

Inventive Principle:
Principle #15Dynamics

2Device complexity

If verification logic is executed on local processor, then device complexity is reduced, but productivity and verification speed deteriorate

Engineering Contradiction:
Improvesystem complexityVSAvoidmessage verification throughput
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The verification logic is segmented into two parts: software verification for standard messages and hardware verification for critical messages. This segmentation allows the system to handle the majority of messages through software (maintaining low complexity) while offloading only necessary verification tasks to hardware (improving throughput for critical operations).

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A smart dispatcher acts as an intermediary between the message source and verification logic, routing messages to appropriate verification paths. This mediator optimizes the balance between software and hardware verification, ensuring that hardware resources are utilized efficiently to boost productivity without requiring all messages to go through hardware verification.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Speed

If dedicated hardware verification is used, then verification speed is improved, but loss of time due to hardware bottlenecks worsens

Engineering Contradiction:
Improveverification speedVSAvoidmessage transmission delay
Core Design Contradiction:
SpeedVSLoss of time

Solution Approach 1:

Instead of using hardware verification for all messages (excessive action), the system applies hardware verification only to specific message types or under specific conditions (partial action). This selective approach ensures that hardware speed advantages are utilized where needed while avoiding the time loss associated with hardware bottlenecks for routine messages that can be verified faster through software paths.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS20260012428A1Methods and systems for vehicle communication
Publication Date: 2026.01.08 HARMAN INT IND INC
  • US20260012428A1 patent drawing
  • US20260012428A1 patent drawing
  • US20260012428A1 patent drawing

AI summary

Methods and systems are proposed for a communication network. In one example, a system comprises a wireless communication network comprising a verification logic hardware. The system further comprises a processor of a vehicle communicatively coupled to the verification logic hardware, wherein the processor comprises instructions stored on non-transitory memory thereof that when executed enable the processor to determine a message type of a message, and distribute the message to a first queue of a verification logic software of the processor or to a second queue of the verification logic hardware.