Valid-Gated Read Circuitry for Low Power Memory Arrays
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Array structures with valid states unnecessarily consume power during invalid read and write operations due to unnecessary toggling of circuitry, which is particularly problematic in low-power applications like battery-powered devices, leading to increased power consumption and shorter battery life.
Innovation Solution
Implementing valid-gated read and write circuitry that conditionally gates read and write wordlines and latch clocks based on the validity of data, preventing unnecessary toggling unless the data has a valid state or a forced signal is asserted, thereby reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If valid-gated read and write circuitry is implemented to conditionally gate wordlines and latch clocks, then power consumption is reduced during invalid operations, but device complexity increases
Solution Approach 1:
The memory array is segmented into multiple independently controllable rows, each with its own valid-gated read and write circuitry. This allows selective gating of individual row circuits based on validity bits, enabling power reduction at the row level while maintaining overall array functionality.
Solution Approach 2:
Validity bits are pre-stored in each memory row to indicate the validity state of data before read or write operations occur. This preliminary information is used by the gated circuitry to determine whether to activate wordlines and latch clocks, preventing unnecessary toggling before it happens.
Solution Approach 3:
Valid-gated read and write circuitry act as intermediary control layers between the control logic and the physical memory cells. These intermediaries use validity bits to conditionally enable or disable signal paths, thereby reducing power consumption without affecting the core memory storage function.
2Loss of energy
If conditional gating of read and write operations is implemented, then unnecessary toggling of wordlines and latch clocks is prevented, but the control logic complexity increases
Solution Approach 1:
The validity check logic is merged with the existing read and write control logic. The gated read circuitry combines the validity bit check with the read enable signal, and the gated write circuitry combines the validity bit check with the write enable signal, creating unified control paths that reduce overall logic complexity.
Solution Approach 2:
Each memory row is self-sufficient with its own validity bit and gated control circuitry. The validity bit in each row automatically determines whether that row's wordline and latch clock should be activated, eliminating the need for centralized control logic to manage each row individually.
3Duration of action of stationary object
If valid-gated circuitry is used to block unnecessary signal toggling, then battery life is extended, but manufacturing complexity increases
Solution Approach 1:
The patent changes the operational parameters of the memory circuit by introducing validity bits and conditional gating control. This allows the same physical hardware to operate in different power states (active or gated) based on data validity, extending battery life without requiring different hardware for different modes.
Solution Approach 2:
The gated circuitry enables periodic activation of wordlines and latch clocks only when valid data is present. Instead of continuous toggling, the circuitry activates signals periodically based on the validity bit state, reducing average power consumption while maintaining manufacturing simplicity.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
In an array that qualifies each row according to a valid/invalid state, each row may each include valid-gated read circuitry to conditionally block a read wordline from toggling unless the row stores a data word that has a valid state or a read force signal is asserted. Furthermore, in a write operation, each row may have valid-gated write circuitry that conditionally blocks a write wordline from toggling unless input data to be written to the row has a valid state or a write force signal is asserted. Moreover, output latch clocking may be blocked from toggling unless a row to be read stores a data word that has a valid state or the read force signal is asserted, and input latch clocking may also be blocked unless the input data to be written has a valid state or the write force signal is asserted.