Sparse Matrix Data Loading for RAW-Safe Systolic Multiplication

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Solution Overview

Problem

Existing data processing devices face inefficiencies and malfunctions when performing multiplication between matrices, particularly with sparse matrices, due to irregular non-zero components and indices, leading to issues like RAW hazards in systolic array structures.

Innovation Solution

A data processing device and method that includes a storage module to store matrix entries and position information, a data load module to generate a validity mask and instruction sequence based on entry values, and a processing unit to perform operations using non-zero entries, optimizing matrix multiplication by generating efficient instruction sequences for systolic arrays.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a systolic array structure is used for matrix multiplication, then data delivery and reuse among adjacently arranged operation elements is enabled, but malfunctions such as RAW hazards occur when processing sparse matrices with irregular non-zero components and indices

Engineering Contradiction:
Improveoperation correctnessVSAvoiddata delivery control complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by generating an instruction sequence before the actual matrix multiplication operation. The data load module pre-processes the first matrix to create a validity mask and instruction sequence that identifies non-zero entries and their positions, allowing the systolic array to execute operations in advance with proper hazard prevention mechanisms built into the instruction flow

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces an intermediary mechanism through the data load module that acts as a mediator between the storage module and the processing unit. This intermediary generates the validity mask and instruction sequence, which serves as a control layer to manage data delivery and prevent RAW hazards in the systolic array when processing sparse matrices

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If all matrix entries are processed in a systolic array, then complete matrix multiplication is achieved, but resource consumption increases due to processing zero entries unnecessarily

Engineering Contradiction:
Improvematrix multiplication speedVSAvoidprocessing resource consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent extracts only the necessary information (non-zero entries) from the complete matrix by generating a validity mask that identifies zero entries. The instruction sequence then extracts only the non-zero entries for processing, allowing the systolic array to skip zero entries entirely and process only the essential data, thereby reducing resource consumption while maintaining productivity

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent applies local quality by treating different entries in the matrix differently based on their values. Through the validity mask, the system identifies which entries are non-zero and directs processing resources specifically to those locations, rather than uniformly processing all entries. This localized approach optimizes resource utilization by focusing computational effort only where needed

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS12493665B2Device and method for operation of data
Publication Date: 2025.12.09 REBELLIONS INC
  • US12493665B2 patent drawing
  • US12493665B2 patent drawing
  • US12493665B2 patent drawing

AI summary

The present disclosure relates to a data processing device. The data processing device includes: a storage module configured to store a plurality of entries included in a first matrix and position information associated with each of the plurality of entries; a data load module configured to receive the plurality of entries and position information from the storage module, generate a determination result as to whether each of the received entries is zero, and generate an instruction sequence based on the determination result and the position information; and a processing unit configured to generate an operation result by using some of the plurality of entries in accordance with the instruction sequence.