Valley Current Limit Circuit Using Sample-and-Hold Reference

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Solution Overview

Problem

Existing buck converters require lossy sense resistors or complex circuitry to detect and limit valley current, which can lead to inefficiencies and instability.

Innovation Solution

A valley current limit circuit using a sample and hold capacitor, sense FET, and phase generator to generate a negative reference voltage without requiring a lossy sense resistor or complex circuitry, by leveraging the dual phase nature of switching converters.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If lossy sense resistors are used to detect valley current, then current detection is achieved, but energy efficiency deteriorates

Engineering Contradiction:

Improvevalley current detection accuracyVSAvoidenergy efficiency

Core Design Contradiction:

Measurement precisionVSLoss of energy

Solution Approach 1:

The patent extracts the current sensing function from the power path by using a separate sense FET (transistor 210) with its own dedicated sense node. This allows valley current detection without placing resistors in the main current path, eliminating the energy loss associated with sense resistors while maintaining detection accuracy.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces a sample and hold capacitor (220) as an intermediary element that captures and stores the valley current information during the low-side FET ON state. This capacitor acts as a mediator between the sense FET and the control circuitry, enabling accurate valley current detection without requiring continuous power dissipation through resistors.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Measurement precision

If complex circuitry is used to generate negative reference voltage, then valley current limit detection is achieved, but device complexity increases

Engineering Contradiction:

Improvevalley current limit detection accuracyVSAvoidcircuit complexity

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The patent employs periodic switching of the low-side FET to alternately connect the sample and hold capacitor to ground (during ON state) and to the comparator (during OFF state). This periodic action naturally generates the negative reference voltage at the appropriate times without requiring complex dedicated circuitry, simplifying the overall design while maintaining detection accuracy.

Inventive Principle:

Principle #19Periodic action

Solution Approach 2:

The sample and hold capacitor serves multiple functions: it acts as a voltage reference for the comparator, stores valley current information, and generates the negative reference voltage needed for accurate detection. This multi-functionality reduces the need for separate dedicated circuits, thereby reducing overall device complexity.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentEP4625790A1Valley current limit detection scheme for switching regulators

Publication Date: 2025.10.01 NEXPERIA BV

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AI summary

A valley current limit circuit of a switching regulator is provided, with the valley current limit circuit including a sample and hold capacitor. The valley current limit circuit is arranged to charge the sample and hold capacitor when a low-side switch of the switching regulator is OFF and to provide a negative reference voltage from the sample and hold capacitor when the low-side switch is ON. The valley current limit circuit includes a comparator arranged to provide a current limit reference by comparing the negative reference voltage against a switch node voltage of the switching regulator when the low-side switch is ON.