Valley Track Reads for Low-Overhead Memory Cell Refresh

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Solution Overview

Problem

Periodic background scans in memory systems often result in unnecessary additional reads, degrading memory cells and increasing latency and complexity due to complex processes like calculating voltage threshold distributions, which can lead to inefficient memory cell refresh and potential data loss.

Innovation Solution

Implementing a valley track procedure with two calibrations: a coarse calibration to determine an initial bit error count using a default read voltage, followed by a fine calibration to apply a specific read voltage based on mapping information, allowing a single read operation to decide on memory cell refresh, thereby reducing the total number of reads.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If periodic background scans perform multiple additional reads to check memory cell health, then measurement precision of memory cell status is improved, but device complexity and loss of time increase due to unnecessary reads and complex processing

Engineering Contradiction:
Improvememory cell status detection accuracyVSAvoidscan overhead and latency
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent applies preliminary action by performing a first read operation at a first voltage level to obtain initial bit error count information before performing the second read operation at a second voltage level. This preliminary reading allows the system to determine whether the memory cells require intensive inspection, thereby avoiding unnecessary additional reads and reducing scan overhead while maintaining detection accuracy when needed.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If multiple additional reads are performed during background scans, then reliability of memory cell status determination is improved, but manufacturing precision of memory cells degrades due to increased write/erase cycles

Engineering Contradiction:
Improvememory cell status determination accuracyVSAvoidmemory cell degradation
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The system performs a preliminary read at a first voltage level to assess memory cell health before committing to multiple additional reads. This preliminary assessment acts as a filter that prevents unnecessary intensive reading cycles from degrading memory cells, while still ensuring reliable status determination when the preliminary check indicates potential issues.

Inventive Principle:
Principle #10Preliminary action

3Measurement precision

If complex processes like calculating voltage threshold distributions are performed, then measurement precision of memory cell states is improved, but device complexity increases

Engineering Contradiction:
Improvevoltage threshold detection accuracyVSAvoidprocessing complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent uses a preliminary read operation to gather initial bit error count information that simplifies subsequent processing. By obtaining this preliminary data first, the system can determine whether complex voltage threshold distribution calculations are necessary, thereby reducing overall processing complexity while maintaining measurement precision when required.

Inventive Principle:
Principle #10Preliminary action

4Reliability

If multiple additional reads are performed to check memory cells, then reliability of error detection is improved, but loss of time increases due to extended scan duration

Engineering Contradiction:
Improveerror detection accuracyVSAvoidmemory system throughput
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The system performs a preliminary read at a first voltage level to quickly assess memory cell health status before initiating extensive additional reads. This preliminary action serves as an efficient filter that maintains high error detection reliability for problematic cells while significantly reducing the overall time spent on background scans and improving memory system throughput.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20250355743A1Valley track reads to reduce memory system scan overhead
Publication Date: 2025.11.20 MICRON TECHNOLOGY INC
  • US20250355743A1 patent drawing
  • US20250355743A1 patent drawing
  • US20250355743A1 patent drawing

AI summary

Methods, systems, and devices for valley track reads to reduce memory system scan overhead are described. A memory system may use a valley track procedure to perform an initial scan of one or more memory cells and determine whether to refresh the one or more memory cells. In some cases, the valley track procedure may include at least two calibrations, where a coarse calibration associated with a default read voltage may indicate an entry of mapping information, and a fine calibration may use the entry to determine a read voltage. The fine calibration may include application of the read voltage to the one or more memory cells to determine a bit error count (BEC). The memory system may determine whether to refresh the one or more memory cells based on the BEC and a threshold BEC.