Value List Caching for Network Test Packet Generation
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Solution Overview
Problem
The existing methods for generating test packets in network test devices face memory access bandwidth limitations due to the use of dynamic random access memory (DRAM), which is slower than static random access memory (SRAM), leading to increased memory access costs and inefficiencies.
Innovation Solution
Implementing value list caching in network test devices, where value lists are stored in DRAM and portions are read into per-port caches, with per-port stream engines draining and refilling caches to maintain continuous packet transmission, using a cache refill algorithm to prevent starvation and optimize memory access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If DRAM is used to store value lists to reduce memory costs, then memory cost is reduced, but memory access bandwidth becomes insufficient leading to packet transmission bottlenecks
Solution Approach 1:
The patent divides the memory system into two segments: DRAM for bulk storage of value lists and SRAM caches for frequently accessed portions. This segmentation allows the system to leverage the cost advantage of DRAM while maintaining high-speed access through SRAM, resolving the contradiction between memory cost and access bandwidth.
Solution Approach 2:
The patent implements a nested memory architecture where SRAM caches are embedded within the packet generation pipeline that accesses DRAM-stored value lists. The SRAM caches contain nested copies of frequently used value list portions, creating a hierarchical structure that provides fast access to critical data while maintaining comprehensive storage in DRAM.
2Productivity
If SRAM is used to store value lists to improve memory access bandwidth, then packet transmission rate is improved, but memory cost increases significantly
Solution Approach 1:
The patent applies local quality by providing high-speed SRAM caching only for the portions of value lists that are frequently accessed during packet generation, while less frequently accessed data remains in DRAM. This selective application of high-performance memory to critical data paths achieves high bandwidth where needed without the prohibitive cost of universal SRAM deployment.
3Productivity
If value lists are read from DRAM for each packet generation, then memory access bandwidth bottleneck occurs, but using caches increases device complexity
Solution Approach 1:
The patent implements preliminary action by pre-loading value list portions into SRAM caches before they are needed for packet generation. The system proactively manages cache contents and refills them in advance, eliminating the need for complex real-time memory arbitration during packet transmission and simplifying the overall control logic.
Solution Approach 2:
The packet generation engine is enhanced to self-service from the SRAM caches, automatically accessing cached value lists without requiring complex external memory management intervention. This self-service capability reduces the burden on external control systems and simplifies the overall device architecture.
Data Source
AI summary
Methods, systems, and computer readable media for generating test packets in a network device using value lists caching are disclosed. In one method, value lists are stored in dynamic random access memory of a network test device. Each value lists includes values for user defined fields (UDFs) to be inserted in test packets. Portions of each value lists are read into per-port caches. The UDF values are drained from the per-port caches using per-port stream engines to generate and send streams of test packets to one or more devices under test. The per-port caches are refilled with portions of the value lists from the DRAM and a rate sufficient to maintain the sending of the stream engine packets to the one or more devices under test.