Varactor With Through-Wafer Vias for Capacitance Control
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Solution Overview
Problem
The production of varactors with through-wafer via structures is complex and requires multiple masks and process steps, increasing manufacturing costs and inefficiencies in high-speed circuit applications.
Innovation Solution
A varactor design incorporating a substrate with through-wafer vias and conductive materials forming capacitors between these vias, where the capacitance is adjustable via bias voltage, allowing for efficient integration and reduced front-end process areas by utilizing back-end processes for passive device formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional varactor production methods are used, then varactors can be manufactured, but the production process becomes complex requiring multiple masks and process steps
Solution Approach 1:
The patent merges the formation of through-wafer vias and varactor structures into a unified process flow. The via holes are formed first, then the same via holes are used as the basis for varactor formation by adding doped regions and conductive layers, eliminating the need for separate mask and process steps for varactor fabrication.
Solution Approach 2:
The through-wafer vias serve multiple functions: they act as structural interconnects for stacking chips/wafers and simultaneously serve as the electrode structures for varactor devices. This multi-functionality reduces the need for dedicated varactor fabrication processes.
2Ease of manufacture
If traditional varactor production methods are used, then varactors can be manufactured, but manufacturing costs increase
Solution Approach 1:
The patent combines varactor fabrication with the standard through-wafer via formation process, so that varactors are created as part of the normal interconnect fabrication sequence rather than requiring additional expensive fabrication steps.
Solution Approach 2:
The existing via structures and doped regions automatically form the varactor components without requiring additional processing. The depletion region forms naturally between adjacent doped regions in the via, eliminating the need for separate varactor structure creation.
3Productivity
If front-end processes are used for passive devices, then passive devices can be formed, but expensive front-end process areas are consumed
Solution Approach 1:
The patent moves passive device fabrication from the front-end process dimension to the back-end process dimension by forming varactors after the main active devices are completed, utilizing the same substrate and via structures in a sequential manufacturing approach.
Solution Approach 2:
The back-end processes, originally intended only for interconnect formation, are made universal by adding varactor fabrication capabilities, allowing the same process area to produce both active devices and passive devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design simplifies the manufacturing process, reduces costs, and enhances the integration and efficiency of varactors in high-speed circuits by leveraging the back-end processes for passive device integration and capacitance control through bias voltage adjustments.
Implementation Method 1
A capacitance of a depletion-region capacitor between the first through-wafer via and the second through-wafer via is determined by a bias voltage applied to the first through-wafer via and the second through-wafer via
Data Source
AI summary
A varactor is provided. A substrate includes a first surface, a second surface and a first opening and a second opening in the substrate. A conductive material is filling the first and second openings, to form a first through-wafer via (TWV) and a second through-wafer via. A first capacitor is coupled between the first through-wafer via and a first terminal. A second capacitor is coupled between the second through-wafer via and a second terminal. A capacitance of a depletion-region capacitor between the first through-wafer via and the second through-wafer via is determined by a bias voltage applied to the first through-wafer via and the second through-wafer via.