Varactor and Transistor Gate Stack Work Function Tuning
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Solution Overview
Problem
The existing manufacturing process for MOS capacitors with high zero-referenced tunability is complex due to the need for multiple masks and ion implantation steps, which complicates the doping of gate electrodes differently than highly doped semiconductor regions, leading to potential inadvertent doping errors.
Innovation Solution
A semiconductor structure and method involving a gate-first process with a gate stack including a high-k dielectric gate insulation material and work function adjustment metal, where the same work function adjustment metal is used for both the varactor and field effect transistor, allowing for self-aligned doping and eliminating the need for trench isolations between highly doped regions, thereby simplifying the process and reducing errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple masks and ion implantation steps are used to dope gate electrodes differently than highly doped semiconductor regions, then zero-referenced tunability of capacitance is improved, but manufacturing complexity increases
Solution Approach 1:
The patent combines the gate electrode and highly doped semiconductor regions into a single continuous doping step using one mask, eliminating the need for multiple separate ion implantation steps. This merging approach maintains the ability to achieve different doping levels in different regions while significantly reducing manufacturing complexity and the number of process steps required.
Solution Approach 2:
The single mask serves multiple functions: it defines both the gate electrode pattern and the highly doped semiconductor region pattern simultaneously. This universal masking approach eliminates the need for separate masks for each doping step, reducing the total number of lithography and alignment operations required in the manufacturing process.
2Adaptability or versatility
If multiple masks and ion implantation steps are used to dope gate electrodes differently than highly doped semiconductor regions, then zero-referenced tunability of capacitance is improved, but risk of inadvertent doping errors increases
Solution Approach 1:
The patent combines the gate electrode and highly doped semiconductor regions into a single continuous doping step using one mask, eliminating the need for multiple separate ion implantation steps. This merging approach maintains the ability to achieve different doping levels in different regions while significantly reducing manufacturing complexity and the number of process steps required.
Solution Approach 2:
The patent converts the potential harm of complex multi-step doping processes into a benefit by using a single unified doping step. This approach eliminates the accumulation of errors that can occur during multiple sequential operations, thereby improving doping accuracy and reducing the risk of inadvertent doping errors while maintaining the desired different doping levels.
3Manufacturing precision
If trench isolations are formed below sidewalls of gate electrode, then doping precision is improved, but device complexity increases
Solution Approach 1:
The patent extracts and eliminates the trench isolation structure from the device architecture. By removing this additional structural element, the patent simplifies the overall device complexity while maintaining precise doping control through the self-aligned nature of the single mask approach, where the mask edges automatically define the doping boundaries without requiring physical trenches.
Solution Approach 2:
The patent employs self-aligned doping where the mask structure itself serves to define the doping regions without requiring additional isolation structures. The mask edges automatically create precise doping boundaries through the ion implantation process, eliminating the need for trench isolations and reducing structural complexity while maintaining high doping precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables high zero-referenced tunability of capacitance using only one polarity of gate voltage, reducing manufacturing complexity and avoiding inadvertent doping issues, while maintaining high capacitance tuning range.
Implementation Method 1
The application of the gate voltage may create an electric field in the body region, which may have an influence on the distribution of charge carriers in the body region
Implementation Method 2
The doping of the gate electrode may have an influence on the Fermi energy of electrons in the gate electrode, which may lead to a bending of the valance band and the conduction band of the semiconductor material of the body region in the vicinity of the gate electrode
Data Source
AI summary
A semiconductor structure includes a varactor and a field effect transistor. The varactor includes a body region that includes a semiconductor material and a first gate structure over the body region. The body region is doped to have a first conductivity type. The first gate structure includes a first gate insulation layer and a first work function adjustment metal layer. The field effect transistor includes a source region, a channel region, a drain region and a second gate structure over the channel region. The source region and the drain region are doped to have a second conductivity type that is opposite to the first conductivity type. The second gate structure includes a second gate insulation layer and a second work function adjustment metal layer. The first work function adjustment metal layer and the second work function adjustment metal layer include substantially the same metal.