Variable Accuracy Parasitic Capacitance Extraction for IC Timing
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Solution Overview
Problem
Current parasitic capacitance extraction tools face challenges in achieving a reasonable accuracy versus runtime trade-off, particularly in high-speed and high-precision integrated circuit design, where estimating wire capacitance is difficult due to its varying and complex nature, leading to potential inaccuracies in circuit behavior prediction.
Innovation Solution
The method employs variable accuracy parasitic capacitance extraction based on circuit sensitivity, prioritizing high accuracy for critical nets and lower accuracy for non-critical nets, tailoring the calculation accuracy to timing uncertainty rather than capacitance uncertainty to optimize runtime and accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If high accuracy parasitic capacitance extraction is performed for all nets, then measurement precision is improved, but productivity deteriorates due to large computation requirements
Solution Approach 1:
The patent applies local quality by differentiating extraction accuracy based on net criticality. Critical nets (those affecting timing closure) receive high accuracy extraction, while non-critical nets receive lower accuracy extraction. This is implemented by classifying nets into critical and non-critical groups and applying different extraction algorithms or accuracy levels to each group, thereby optimizing the balance between overall accuracy and runtime.
Solution Approach 2:
The patent applies partial action by performing high accuracy extraction only on the subset of critical nets that actually require it for timing closure, rather than uniformly applying high accuracy to all nets. This selective approach reduces total computation time while maintaining sufficient accuracy for the nets that matter most to circuit performance.
2Productivity
If lower accuracy parasitic capacitance extraction is used, then productivity is improved with faster computation, but measurement precision deteriorates with potential inaccuracies in circuit behavior prediction
Solution Approach 1:
The patent ensures that critical nets - those whose accuracy directly impacts circuit behavior prediction - receive high accuracy extraction. Non-critical nets use lower accuracy extraction since they have minimal impact on overall circuit behavior. This local differentiation maintains prediction accuracy for critical paths while improving overall runtime.
Solution Approach 2:
The patent applies high accuracy extraction only partially - specifically to critical nets that require it for accurate circuit behavior prediction. This selective high accuracy approach avoids the runtime penalty of uniform high accuracy extraction while ensuring that the nets most important to prediction accuracy are treated with sufficient precision.
3Measurement precision
If uniform high accuracy extraction is applied to all nets, then measurement precision is improved, but loss of time increases due to unnecessary computation on non-critical nets
Solution Approach 1:
The patent identifies and classifies nets into critical and non-critical categories based on their impact on timing closure. Critical nets receive high accuracy extraction to ensure precise measurement, while non-critical nets receive lower accuracy extraction. This local quality differentiation eliminates unnecessary high accuracy computation on nets that do not affect timing closure, reducing total computation time.
Solution Approach 2:
The patent applies high accuracy extraction only to the extent necessary - specifically to critical nets that require it for timing closure. By performing high accuracy extraction only partially on the subset of nets that actually need it, the patent avoids the time loss associated with uniformly applying high accuracy to all nets, including those where such precision is unnecessary.
Data Source
AI summary
The method of this invention determines the timing of an integrated circuit design. At each node, the method determines if the timing of signal propagation at that node is critical. If this timing is critical, method calculates the capacitance at said current node using a highly accurate but computationally intensive model. If this timing is not critical, the method uses a less accurate but less computationally intensive model. The method calculates a signal delay for each node from the drive strength, calculated capacitance and fan-out. This signal delay is compared to a design goal. This method achieves a better trade-off between timing determination run-time and accuracy. Timing criticality can be determined from one or more of conductor length/area, fan-out, logic depth and timing slack.