Frequency Synthesizer with Variable Accuracy Codes for Clock Drift
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Solution Overview
Problem
Conventional low-frequency clock signals have fixed accuracy due to a fixed resolution of the control signal, making it difficult to correct drift and cycle-to-cycle jitter, which limits the tunability of frequency synthesizers.
Innovation Solution
A frequency synthesizer architecture that includes a digitally-controlled oscillator and delta-sigma modulation circuit, allowing for tunable accuracy of the output clock frequency, adjustable power consumption, and rapid convergence, using multistage operations and variable accuracy codes to generate a low-speed clock signal with long-term accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a fixed resolution control signal is used by the oscillator, then the oscillator can be controlled with simple circuitry, but the accuracy of the low frequency clock signal becomes fixed and cannot correct drift and jitter
Solution Approach 1:
The patent implements a variable resolution control mechanism where the resolution of the control signal to the oscillator is dynamically adjusted based on the desired accuracy level. The system can switch between different resolution modes (e.g., first resolution for high accuracy, second resolution for lower accuracy) allowing the accuracy of the low frequency clock signal to be tuned while managing circuit complexity through controlled dynamic adjustment rather than fixed high-resolution control.
Solution Approach 2:
The system changes the resolution parameter of the control signal to match the required accuracy level. When high accuracy is needed, the control signal uses a finer resolution to correct drift and jitter; when lower accuracy suffices, the resolution is coarsened to reduce complexity. This parameter adaptation allows the frequency synthesizer to optimize between accuracy and complexity based on application requirements.
2Measurement precision
If high accuracy is achieved through fine control signal resolution, then drift and jitter can be corrected, but power consumption increases
Solution Approach 1:
The patent applies partial action by using high-resolution control signals only when and where needed to correct accuracy errors, rather than continuously applying maximum resolution. The system monitors the actual accuracy requirements and applies fine control adjustments only during periods or conditions where high precision is necessary, reducing overall power consumption while maintaining required accuracy levels.
Solution Approach 2:
The control signal resolution is dynamically adjusted based on the required accuracy level. The system can switch between high-resolution mode (higher power consumption) and low-resolution mode (lower power consumption) depending on the application's accuracy requirements, allowing optimization of the power-accuracy tradeoff in real-time based on operational conditions.
3Adaptability or versatility
If variable accuracy codes are used to achieve tunable accuracy, then the frequency synthesizer becomes more versatile, but the device complexity increases
Solution Approach 1:
The patent implements a multi-functional control architecture where a single control circuit can operate with multiple resolution modes and accuracy levels. The same hardware infrastructure supports both high-accuracy and low-accuracy operation by accepting variable accuracy codes that specify the desired resolution level. This universal design allows the frequency synthesizer to serve multiple application requirements without requiring separate dedicated circuits for each accuracy level.
Data Source
AI summary
An apparatus includes a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate a first code by counting a number of cycles of an input clock signal in a period determined by (i) an output clock signal and (ii) a second code. The second code may be variable. The second circuit may be configured to generate a third code by a delta-sigma modulation of the first code. The third circuit may be configured to generate the output clock signal (i) in response to the third code and (ii) within an accuracy determined the second code.