Variable-Resolution ADC Equalization for Low-Loss Channel Power Savings
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing digital data communication systems face inefficiencies in power consumption due to the need for full-resolution analog-to-digital conversion and processing across all channels, even when channel loss is low, leading to unnecessary power usage.
Innovation Solution
Implementing a variable resolution analog-to-digital converter (ADC) and processing logic that dynamically adjusts the number of bits based on channel attenuation, reducing power consumption by disabling unused bits and logic sub-blocks in lower resolution modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If full-resolution ADC and processing logic are used for all channels, then link performance is maintained, but power consumption increases
Solution Approach 1:
The patent applies dynamics by making the ADC resolution and processing logic configuration adjustable based on channel conditions. The system dynamically switches between full-resolution and reduced-resolution modes according to channel attenuation levels, allowing optimal power-performance tradeoff. Specifically, the ADC can operate at different bit resolutions (e.g., 6-bit or 8-bit) depending on whether the channel attenuation is below or above a threshold, and processing logic sub-blocks are selectively enabled or disabled based on the active resolution mode.
Solution Approach 2:
The patent changes the resolution parameter of the ADC and the configuration of processing logic based on channel attenuation measurements. When channel attenuation is low, the system uses reduced resolution (fewer bits) and disables certain processing logic sub-blocks to save power. When attenuation is high, full resolution and all processing blocks are activated to maintain link performance. This parameter adaptation resolves the contradiction by matching resource usage to actual channel conditions.
2Use of energy by moving object
If variable resolution ADC and processing logic are implemented, then power consumption is reduced, but device complexity increases
Solution Approach 1:
The patent segments the processing logic into multiple independent sub-blocks (e.g., first processing sub-block, second processing sub-block) that can be selectively enabled or disabled based on resolution mode. The ADC is also segmented into different resolution configurations. This segmentation allows the system to activate only the necessary portions of the logic for the current channel conditions, managing complexity through modular design while enabling power savings through selective deactivation.
Solution Approach 2:
The patent designs the ADC and processing logic to be multi-functional, capable of operating in multiple resolution modes (e.g., 6-bit mode, 8-bit mode) and supporting different channel conditions with a single hardware implementation. The same physical hardware structure serves multiple functions by dynamically reconfiguring its operation, avoiding the need for separate dedicated circuits for each resolution level and thereby managing overall device complexity.
3Measurement precision
If full processing resolution is used, then measurement precision is maintained, but unnecessary processing occurs when channel loss is low
Solution Approach 1:
The patent applies partial action by using only the necessary processing resolution required for the current channel conditions. When channel attenuation is low, reduced processing resolution (fewer bits processed) is sufficient to maintain link performance, so the system deliberately uses partial processing rather than full resolution. This avoids unnecessary processing operations while maintaining adequate precision for the given channel quality, thereby improving processing efficiency.
Data Source
AI summary
A receiver includes a variable resolution analog-to-digital converter (ADC) and variable resolution processing logic/circuitry. The processing logic may use feed-forward equalization (FFE) techniques to process the outputs from the ADC. When receiving data from a channel having low attenuation, distortion, and/or noise, the ADC and processing logic may be configured to sample and process the received signal using fewer bits, and therefore less logic, than when configured to receiving data from a channel having a higher attenuation, distortion, and/or noise. Thus, the number of (valid) bits output by the ADC, and subsequently processed (e.g., for FFE equalization) can be reduced when a receiver of this type is coupled to a low loss channel. These reductions can reduce power consumption when compared to operating the receiver using the full (i.e., maximum) number of bits the ADC and processing logic is capable of processing.