Variable Execution-Time Atomic Operations with Adaptive Cache Locking

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Solution Overview

Problem

Existing memory device designs struggle to efficiently handle both short and long execution time atomic operations (AMOs) in a single memory side cache, leading to performance issues due to the difficulty in accommodating varying run-times of these operations.

Innovation Solution

Implementing a cache system with a results queue and credit-based mechanism to manage long AMOs by locking cache lines during execution and using a results queue, while allowing short AMOs to execute without locking, thereby maintaining efficiency for both types of operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a single memory side cache is used to handle both short and long AMOs, then the cache structure is simple, but performance deteriorates due to inability to accommodate varying run-times

Engineering Contradiction:
Improvecache structureVSAvoidAMO processing performance
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent segments the cache handling mechanism into two distinct paths: one for short AMOs that can complete within a single cycle, and another for long AMOs that require multiple cycles. This is achieved by evaluating the run length of each AMO and routing it through appropriate execution paths, thereby resolving the performance issue while maintaining reasonable structural complexity

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces dynamic handling of AMOs by evaluating their run length at execution time. Short AMOs are executed immediately without locking, while long AMOs trigger cache line locking and result queuing. This dynamic adaptation allows the system to optimize performance based on the specific characteristics of each AMO, resolving the contradiction between simplicity and performance

Inventive Principle:
Principle #15Dynamics

2Reliability

If cache line locking is applied to all AMOs, then atomicity is ensured, but productivity decreases due to cache line contention

Engineering Contradiction:
ImproveatomicityVSAvoidAMO execution throughput
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies cache line locking selectively rather than uniformly to all AMOs. Specifically, locking is applied only to long AMOs that require multiple cycles to complete, while short AMOs execute without locking. This localized application of the locking mechanism maintains atomicity where needed while minimizing contention, thereby resolving the contradiction between reliability and productivity

Inventive Principle:
Principle #3Local quality

3Productivity

If short AMOs are allowed to execute without locking, then productivity increases, but reliability may be compromised for long AMOs

Engineering Contradiction:
ImproveAMO execution speedVSAvoidatomicity guarantee
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent dynamically determines the execution strategy for each AMO based on its run length evaluation. Short AMOs are executed without locking to maximize throughput, while long AMOs trigger the locking protocol to ensure atomicity. This dynamic decision-making process allows the system to optimize for productivity when safe and ensure reliability when necessary, resolving the contradiction between these two parameters

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS12367148B2Variable execution time atomic operations
Publication Date: 2025.07.22 MICRON TECHNOLOGY INC
  • US12367148B2 patent drawing
  • US12367148B2 patent drawing
  • US12367148B2 patent drawing

AI summary

System and techniques for variable execution time atomic operations are described herein. When an atomic operation for a memory device is received, the run length of the operation is measured. If the run length is beyond a threshold, a cache line for the operation is locked while the operation runs. A result of the operation is queued until it can be written to the cache line. At that point, the cache line is unlocked.