Variable-T BCH Encoder Reuse for Lower XOR Array Overhead
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Solution Overview
Problem
Conventional BCH encoding technologies require a large number of XOR arrays and consume significant power due to the need for multiple settings of error correction strength, which leads to inefficient circuit implementation and increased power consumption in flash storage media.
Innovation Solution
The implementation of variable T Bose-Chaudhuri-Hocquenghem (BCH) encoding, which reduces the number of XOR arrays and reuses BCH encoders to support a range of error correction strengths, allowing for more efficient error correction with reduced circuit size and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional BCH encoding uses multiple XOR arrays to support different error correction strengths, then error correction capability is improved, but circuit area and power consumption increase
Solution Approach 1:
The patent implements a universal BCH encoder that can handle multiple error correction strengths (different T values) using a single circuit structure. The encoder uses a configurable polynomial divider that can process different generator polynomials corresponding to different T values, allowing one circuit to perform multiple error correction functions that previously required separate dedicated circuits for each T value.
Solution Approach 2:
The patent introduces dynamic configurability to the BCH encoder through control logic that selects different generator polynomials and adjusts the polynomial divider parameters based on the desired error correction strength. This dynamic adaptation allows the same hardware to reconfigure itself for different T values, eliminating the need for multiple static encoder circuits.
2Reliability
If conventional BCH encoding uses multiple XOR arrays for different error correction strengths, then decoding performance is improved, but power consumption increases
Solution Approach 1:
The universal BCH encoder uses a single polynomial divider circuit that can be configured to perform divisions with different generator polynomials corresponding to various error correction strengths. This multi-functional approach ensures that the same circuit performs all error correction operations, maintaining full decoding performance across different T values while avoiding the power consumption of multiple dedicated circuits.
Solution Approach 2:
The patent merges multiple separate BCH encoder circuits into a single unified encoder. By combining the functionality of multiple XOR arrays and polynomial dividers into one shared resource with configurable parameters, the system achieves the same error correction performance while significantly reducing the number of active circuit components and their associated power consumption.
3Reliability
If conventional BCH encoding increases error correction strength, then reliability is improved, but implementation complexity increases
Solution Approach 1:
The patent implements dynamic reconfigurability where the encoder's internal parameters (generator polynomial selection, divider coefficients) can be adjusted based on the desired error correction strength. This dynamic approach allows high error correction capability to be achieved through software-controlled configuration rather than hardware complexity, simplifying the physical implementation while maintaining reliability.
Solution Approach 2:
The patent changes the operational parameters of the BCH encoder (specifically the generator polynomial and divisor parameters) to achieve different error correction strengths. By varying these parameters rather than changing the fundamental circuit architecture, the system can adapt to different reliability requirements without increasing implementation complexity.
Data Source
AI summary
A system for implementing variable T BCH encoders includes: a polynomial multiplier for multiplying a message polynomial by a difference polynomial to achieve a first value, wherein the message polynomial comprises data bits as coefficients and the difference polynomial comprises minimal polynomials that are present in a T error correcting code and are absent from a T−ΔT error correcting BCH code; a shifter/zero-padder coupled with the BCH encoder, the shifter/zero-padder for multiplying the first value by xN-{tilde over (K)} to achieve a second value; a BCH encoder coupled with the polynomial multiplier, the BCH encoder for dividing the second value by a generator polynomial of the T error correcting BCH code and calculating a remainder based on the dividing to achieve a third value; and a polynomial divider for dividing the third value by the difference polynomial to achieve a fourth value comprising parity of the T−ΔT error correcting BCH code.