Variable-Bias Delay-Locked Loop for Low-Power Clock Synchronization
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Solution Overview
Problem
Conventional delay-locked loop circuits in semiconductor memory devices consume excessive current in active modes and lack efficient current reduction mechanisms for power-down or self-refresh modes.
Innovation Solution
A delay-locked loop circuit with a variable voltage generator that produces a variable bias voltage signal based on operation modes, allowing the circuit to adjust its operation current, including a phase detector, charge pump, variable delay line, and delay compensation circuit, to synchronize internal and external clock signals while minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the delay-locked loop operates in active mode with sufficient current to maintain clock synchronization, then clock synchronization reliability is improved, but power consumption increases
Solution Approach 1:
The delay-locked loop circuit dynamically adjusts its operation current based on the operation mode of the semiconductor memory device. A mode determining unit identifies whether the device is in active mode, power-down mode, or self-refresh mode, and accordingly controls the current supplied to the delay-locked loop. This dynamic current adjustment maintains reliable clock synchronization in active mode while reducing power consumption in low-power modes.
Solution Approach 2:
The invention changes the current parameter of the delay-locked loop based on operation modes. In active mode, sufficient current is supplied to maintain accurate clock synchronization. In power-down mode and self-refresh mode, the current is reduced to minimize power consumption. This parameter change approach resolves the contradiction between maintaining synchronization reliability and reducing power consumption in different operational states.
2Use of energy by moving object
If the delay-locked loop reduces current in standby modes to save power, then power consumption is reduced, but clock synchronization accuracy may deteriorate
Solution Approach 1:
The circuit dynamically adapts its current level to the specific standby mode. In power-down mode where precise synchronization is less critical, lower current is used. In self-refresh mode where timing accuracy remains important, the circuit maintains higher current levels. This dynamic adaptation ensures that power consumption is minimized without compromising the synchronization accuracy required for each specific mode.
Solution Approach 2:
Different current levels are applied to the delay-locked loop depending on the specific operation mode. The mode determining unit enables the circuit to apply appropriate current quality to each mode: sufficient current for self-refresh mode to maintain timing accuracy, and reduced current for power-down mode where power savings are prioritized. This local quality approach ensures optimal balance between power consumption and synchronization accuracy for each operational state.
Data Source
AI summary
A delay-locked loop circuit comprising a variable voltage generator and a delay-locked loop. The variable voltage generator is configured to generate a variable bias voltage signal in response to a standby signal. The variable bias voltage signal has differing voltage levels according to operation modes. The operation modes include a standby mode and an active mode. The delay-locked loop is configured to generate an internal clock signal in response to the standby signal and the variable bias voltage signal. The internal clock signal is synchronized with an external clock signal.