Variable-Bias Peak Detector for Fast Linear Voltage Tracking
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Solution Overview
Problem
Existing peak detectors in wireless communication devices face challenges in accurately and quickly detecting high peak voltages, leading to potential damage from severe impedance mismatches, due to their limited speed, accuracy, and linearity, especially when dealing with large fast-rising and falling signals.
Innovation Solution
The implementation of a high linear fast peak detector with variable bias current and variable bias voltage, which adjusts the bias current and voltage based on the input signal to improve detection performance, allowing for faster charging and discharging of capacitors and enhanced tracking of voltage peaks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a peak detector is designed to detect high peak voltages quickly, then the detection speed is improved, but the accuracy and linearity deteriorate
Solution Approach 1:
The patent implements dynamic bias adjustment where the bias current and voltage are varied based on the input signal level. During fast transient conditions, higher bias currents are applied to improve response speed, while during steady-state conditions, lower bias currents maintain accuracy and reduce power consumption. This dynamic adaptation resolves the contradiction between speed and accuracy.
Solution Approach 2:
The patent changes operating parameters (bias current and voltage levels) based on signal conditions to optimize detector performance. By adjusting these parameters dynamically, the detector achieves both fast response during transients and high accuracy during steady-state operation, resolving the speed-accuracy tradeoff.
2Speed
If the bias current is increased to improve detection speed, then the response time is reduced, but the power consumption increases
Solution Approach 1:
The patent employs dynamic bias control where the bias current is adjusted in real-time based on signal characteristics. During fast transients requiring quick response, higher bias currents are temporarily applied. During steady-state conditions, the bias current is reduced to minimize power consumption. This dynamic approach resolves the contradiction between response time and power consumption.
Solution Approach 2:
The detector operates with periodic bias adjustment cycles, switching between high-bias mode for fast response and low-bias mode for power savings. This periodic modulation of bias current allows the system to achieve fast response when needed while maintaining low average power consumption during normal operation.
3Measurement precision
If the detector is designed for high sensitivity, then small voltage changes can be detected, but the ability to handle large voltage peaks without saturation deteriorates
Solution Approach 1:
The patent implements dynamic range adaptation through variable biasing and gain control. The detector automatically adjusts its sensitivity and voltage handling capability based on the input signal level. For small signals, high sensitivity mode is activated to detect subtle changes. For large voltage peaks, the detector switches to a mode with reduced sensitivity but extended voltage range, preventing saturation while maintaining the ability to detect significant changes.
Solution Approach 2:
The detector changes its operating parameters (bias voltage, gain settings) based on the amplitude of the input signal. This parameter adaptation allows the system to maintain optimal performance across a wide dynamic range, achieving both high sensitivity for small signals and robust handling of large voltage peaks without saturation.
Data Source
AI summary
A high linear fast peak detector having a variable bias current and/or a variable bias voltage is described. In an exemplary design, the peak detector includes a transistor, a variable current source, a capacitor, and a feedback circuit. The transistor receives the input signal and provides a source current. The variable current source receives the input signal, provides high bias current when the input signal is low, and provides low bias current when the input signal is high. The capacitor is charged by the source current when the input signal is high and is discharged by the high bias current when the input signal is low. The feedback circuit receives a detected signal from the capacitor and provides higher bias voltage for the transistor when the input signal is high, which results in higher source current from the transistor.