Variable Bit-Width Image Processor Bus Architecture
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Solution Overview
Problem
Existing image processing systems face inefficiencies in handling variable-bit image signals, particularly in transmitting and processing multi-bit pixel data, which can lead to waste of bandwidth and inefficient logic processes due to fixed data bus designs.
Innovation Solution
The implementation of an image processing system that includes a codec module and a memory controller, which divide pixel data into more significant bits (M bits) and less significant bits (N bits), allowing for flexible storage and retrieval of these bits across different memory regions, enabling efficient data transfer and processing through a bus configured to support variable bit-widths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a fixed data bus design is used for transmitting pixel data, then the system structure is simple, but bandwidth is wasted and processing efficiency is reduced when handling variable-bit image signals
Solution Approach 1:
The pixel data is segmented into two separate data groups: first data comprising M more significant bits and second data comprising N less significant bits. These segmented data groups are stored in different memory regions and accessed through optimized pathways, allowing the system to handle variable-bit signals efficiently without requiring a completely complex restructured bus system.
Solution Approach 2:
The system dynamically adjusts the number of significant bits (M) and less significant bits (N) based on the specific processing requirements of different image signals. This dynamic configuration allows the data bus to adapt its effective width and bandwidth allocation, optimizing processing efficiency for both high-bit and low-bit signals without requiring a fixed wide bus for all cases.
2Reliability
If all pixel data bits are transmitted and processed, then complete image information is preserved, but bandwidth is wasted when fewer bits are sufficient
Solution Approach 1:
Different quality levels are applied to different bit groups based on their significance. The M more significant bits are transmitted and processed with higher priority and bandwidth allocation, while the N less significant bits are handled with reduced bandwidth. This local quality differentiation ensures that the most important image information is preserved with full fidelity while reducing overall bandwidth consumption.
Solution Approach 2:
The system changes the parameter of bit significance weighting, treating M significant bits and N less significant bits differently in terms of transmission priority and processing resources. This parameter change allows the system to maintain complete image information while optimizing bandwidth utilization by allocating resources according to bit importance rather than treating all bits equally.
3Adaptability or versatility
If the data bus width is increased to handle maximum bit requirements, then all variable-bit signals can be processed, but bandwidth is wasted for signals requiring fewer bits
Solution Approach 1:
The data bus system dynamically configures its effective width and resource allocation based on the actual bit requirements of the incoming signal. When processing signals with fewer bits, the system activates only the necessary data pathways and memory regions, reducing effective bus width and bandwidth consumption. This dynamic adaptation maintains versatility for handling various signal types while eliminating bandwidth waste for lower-resolution signals.
Solution Approach 2:
The segmented data bus architecture with separate storage regions for M-significant bits and N-less significant bits creates a universal system that can handle multiple signal types and bit widths. The same physical infrastructure serves both high-bit and low-bit signals by selectively activating appropriate data groups and memory regions, providing multi-functionality without requiring dedicated bus structures for each signal type.
Data Source
AI summary
An image processing system comprises a first image processing device configured to process a frame of image data comprising a plurality of pixels, each having corresponding pixel values. Each of the pixel values include a first and second set of bits that may be separately or simultaneously accessed and/or processed. The first set of bits may correspond to the more significant bits of each pixel and the second set of bits may correspond to the less significant bits. In some examples the number of bits in each of the first and second set of bits may correspond to the width of a used data bus and/or features of a peripheral device connected to the image processor, such as a display.