Variable Bit Line Bias for Nonvolatile Memory Arrays
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Solution Overview
Problem
As memory cells decrease in size and memory arrays increase in density, maintaining data integrity becomes challenging due to variations in word line voltage caused by resistive-capacitive loading along the word line, leading to broadened threshold voltage distributions and reduced data retention.
Innovation Solution
Each bit line coupled to a memory cell is biased to a voltage that varies based on its distance from the word line driver, compensating for the resistive-capacitive loading and ensuring consistent programming voltage across the word line.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells decrease in size and memory arrays increase in density, then storage capacity is improved, but data integrity deteriorates due to word line voltage variations
Solution Approach 1:
The patent applies local quality by providing different bit line voltages to different regions of the memory array based on their distance from the word line driver. Memory cells closer to the driver receive one voltage level while those farther away receive a different voltage level, compensating for the voltage drop along the word line and maintaining uniform programming conditions across the dense array.
Solution Approach 2:
The patent changes the bit line voltage parameter based on spatial position within the memory array. By adjusting the voltage applied to bit lines according to their location relative to the word line driver, the system compensates for resistive-capacitive loading effects and maintains consistent effective programming voltage across all memory cells despite increased density.
2Device complexity
If uniform bit line voltage is applied to all memory cells, then device complexity is reduced, but threshold voltage distribution broadens leading to reduced data retention
Solution Approach 1:
The patent implements local quality by dividing the memory array into multiple regions and applying different bit line voltages to each region. This spatially differentiated voltage biasing compensates for position-dependent voltage drops along word lines, ensuring that all memory cells experience uniform effective programming voltage, thereby maintaining narrow threshold voltage distributions and improving data retention.
Solution Approach 2:
The patent applies preliminary anti-action by pre-compensating for the expected voltage drop along word lines through differentiated bit line voltage biasing. Before programming occurs, the system calculates and applies appropriate voltage levels to different bit line groups based on their distance from the driver, thereby counteracting the harmful voltage variations that would otherwise broaden threshold distributions and reduce data retention.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach maintains consistent threshold voltage shifts and improves data retention by applying a uniform effective program voltage to all memory cells, reducing the broadening of threshold voltage distributions and minimizing data retention loss across the memory array.
Implementation Method 1
variations in word line voltage caused by resistive-capacitive loading along the word line
Implementation Method 2
variations in word line voltage caused by resistive-capacitive loading along the word line
Data Source
AI summary
An apparatus is provided that includes a word line coupled to a word line driver circuit, bit lines, a plurality of non-volatile memory cells each coupled to the word line and a corresponding one of the bit lines, and a control circuit coupled to the word line and the bit lines. The control circuit is configured to program the memory cells by causing the word line driver to apply a program pulse to the word line, and biasing each bit line to a corresponding bit line voltage that has a value that varies based on a distance between the word line driver and the corresponding bit line.