Variable Bit Storage in 3D NAND Memory Cells
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Solution Overview
Problem
Current memory devices face challenges in optimizing data storage capacity and integration density while maintaining reliable operation and extending lifespan, as the properties of memory cells vary due to differences in word line resistance, leading to inconsistent data storage and potential errors.
Innovation Solution
The memory device incorporates a structure with multiple word lines and channel regions, where the number of bits stored in each memory cell is determined based on the resistive properties of the word lines, allowing for different data storage capacities within a single memory cell string, with memory cells connected to word lines with lower resistance storing more bits and those with higher resistance storing fewer bits, and using a memory controller to manage data distribution accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If data storage capacity is increased to improve integration density, then storage capacity is improved, but reliability deteriorates due to inconsistent word line resistance properties across memory cells
Solution Approach 1:
The patent applies local quality by configuring different memory cells to store different numbers of bits based on their specific word line resistance characteristics. Memory cells connected to word lines with lower resistance store more bits, while those with higher resistance store fewer bits. This localized adaptation to varying resistance properties ensures reliable operation across the entire memory array while maximizing overall storage capacity.
2Quantity of substance
If the number of bits stored in each memory cell is increased, then storage capacity is improved, but manufacturing precision deteriorates due to variations in word line resistance properties
Solution Approach 1:
The patent implements parameter changes by dynamically adjusting the number of bits stored in each memory cell based on the measured resistance characteristics of its associated word line. This parameter adaptation allows the memory system to accommodate manufacturing variations in word line resistance without compromising data storage consistency, as each memory cell is configured according to its specific electrical properties.
3Device complexity
If memory device structure is simplified to reduce complexity, then device complexity is reduced, but adaptability deteriorates because all memory cells must store the same number of bits despite varying word line properties
Solution Approach 1:
The patent applies dynamics by making the memory cell configuration adaptive rather than static. The system dynamically determines the number of bits to store in each memory cell based on real-time measurement of word line resistance properties. This dynamic configuration approach maintains relatively simple device structure while achieving high adaptability to varying electrical characteristics across the memory array.
Data Source
AI summary
A memory device includes word lines stacked on an upper surface of a substrate, channel structures penetrating through the word lines, and each including channel regions connected to one another in a first direction perpendicular to the upper surface of the substrate, and word-line cuts extending in the first direction and dividing the word lines to blocks. The word lines and the channel structures provide memory cell strings, and each of the memory cell strings include memory cells arranged in the first direction. The memory cells included in at least one of the memory cell strings include a first memory cell and a second memory cell disposed at different positions in the first direction, and the number of bits of data stored in the first memory cell is less than the number of bits of data stored in the second memory cell.