Variable Bit-Cell DAC Control for Low-Power High-Fidelity Audio

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Solution Overview

Problem

Wearable audio devices, such as earbuds and headphones, face challenges in achieving high-fidelity audio reproduction while operating in a power-efficient manner due to limited battery capacity.

Innovation Solution

A digital-to-analog converter (DAC) architecture with a variable bit cell array and a control system that adjusts the number of active bit cells based on signal conditions, implemented on a semiconductor die or packaged module, to optimize power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If a DAC architecture with a variable bit cell array is used to dynamically adjust the number of active bit cells based on signal conditions, then power efficiency is improved, but device complexity increases

Engineering Contradiction:
Improvepower consumptionVSAvoidDAC architecture complexity
Core Design Contradiction:
Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The DAC architecture employs a variable bit cell array where the number of active bit cells can be dynamically adjusted based on signal conditions. The control system monitors signal characteristics and activates or deactivates specific bit cells to match the actual signal requirements, enabling the device to adapt its power consumption to the actual audio signal demands rather than operating at fixed maximum capacity

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The invention changes the operational parameters of the DAC by varying the number of active bit cells in the array. By controlling which bit cells are active based on signal conditions, the system can modify its effective resolution and power consumption characteristics dynamically, allowing optimization between power efficiency and audio fidelity based on real-time signal requirements

Inventive Principle:
Principle #35Parameter changes

2Measurement precision

If the number of active bit cells is increased to maintain high-fidelity audio reproduction, then audio quality is improved, but power consumption increases

Engineering Contradiction:
Improveaudio fidelityVSAvoidpower consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The DAC architecture applies partial action by activating only the necessary number of bit cells required for the current signal conditions rather than always operating at full capacity. The control system assesses signal characteristics and enables sufficient bit cells to maintain audio fidelity while leaving remaining bit cells inactive to reduce power consumption, avoiding the excessive action of always using all available bit cells

Inventive Principle:
Principle #16Partial or excessive action

3Use of energy by moving object

If a control system is implemented to dynamically adjust bit cell activation, then power efficiency is improved, but device complexity increases

Engineering Contradiction:
Improvepower consumptionVSAvoidcontrol system complexity
Core Design Contradiction:
Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The control system implements feedback by continuously monitoring signal conditions and using this information to adjust the activation state of bit cells. The system evaluates signal characteristics such as amplitude and complexity, and based on this feedback, dynamically determines the optimal number of active bit cells to maintain audio quality while minimizing power consumption through adaptive control

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS20260058667A1Digital-to-analog converter circuits and related devices
Publication Date: 2026.02.26 SKYWORKS SOLUTIONS INC
  • US20260058667A1 patent drawing
  • US20260058667A1 patent drawing
  • US20260058667A1 patent drawing

AI summary

A digital-to-analog converter (DAC) can include an array having a total number of bit cells, and a control system configured to activate a selected number of the total number of bit cells and to deactivate the remaining bit cells. The selected number can be variable, such that the array consumes a quiescent current that depends on the selected number. The control system can be further configured to change the selected number when a signal condition exceeds a threshold duration.