Variable Bits Per Cell Storage Optimization

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Solution Overview

Problem

Conventional memory sub-systems face inefficiencies in data storage and retrieval due to the trade-offs between storage capacity, read latency, programming speed, and reliability across different types of memory cells, particularly when switching between single-level cells (SLCs) and quad-level cells (QLCs), which affects overall system performance and energy consumption.

Innovation Solution

The memory sub-system dynamically reprograms blocks using different types of memory cells (SLCs, MLCs, TLCs, QLCs, and PLCs) based on access frequency and capacity thresholds, optimizing the number of bits per cell to balance performance, energy consumption, and reliability by initially using SLCs for faster programming and then relocating data to QLCs for higher capacity, while tracking access frequencies and error rates to adjust the type of memory cells used during write operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If SLCs are used for data storage, then programming speed and reliability are improved, but storage capacity is reduced

Engineering Contradiction:
Improveprogramming speedVSAvoidstorage capacity
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The system dynamically switches between SLC and QLC modes based on workload characteristics. Frequently accessed data is stored in SLC for fast programming and retrieval, while less frequently accessed data is stored in QLC to maximize storage capacity. This dynamic adaptation resolves the contradiction by allocating storage resources based on actual usage patterns rather than using a fixed cell type throughout.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

Different portions of the storage device use different memory cell types based on local requirements. The system implements a hybrid architecture where SLC blocks are used for hot data (frequently accessed) and QLC blocks are used for cold data (infrequently accessed). This local differentiation allows each region to optimize for its specific function, achieving both fast programming where needed and high capacity where appropriate.

Inventive Principle:
Principle #3Local quality

2Quantity of substance

If QLCs are used for data storage, then storage capacity is improved, but read latency increases

Engineering Contradiction:
Improvestorage capacityVSAvoidread latency
Core Design Contradiction:
Quantity of substanceVSLoss of time

Solution Approach 1:

The system dynamically migrates data between SLC and QLC storage based on access frequency monitoring. When data is frequently accessed, it is automatically moved to SLC to reduce read latency. When access frequency decreases, data is moved to QLC to free up SLC space for other frequently accessed data. This dynamic management ensures that read latency is minimized for hot data while maintaining high overall storage capacity through QLC usage.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system introduces an intermediary layer (cache or buffer) that manages data movement between SLC and QLC. This intermediary component monitors access patterns and facilitates automatic data migration, acting as a mediator that balances the trade-off between capacity and latency without requiring direct intervention or complex real-time switching logic.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Quantity of substance

If QLCs are used for data storage, then storage capacity is improved, but programming speed decreases

Engineering Contradiction:
Improvestorage capacityVSAvoidprogramming speed
Core Design Contradiction:
Quantity of substanceVSProductivity

Solution Approach 1:

The system dynamically adapts the programming path based on the target storage location. When data needs to be programmed to SLC, the system uses optimized SLC programming routines that achieve high speeds. When data is destined for QLC, the system uses QLC-appropriate programming methods. The dynamic nature of the system ensures that programming operations are always directed to the most appropriate cell type based on current workload demands, thereby maximizing programming speed while utilizing QLC capacity when appropriate.

Inventive Principle:
Principle #15Dynamics

4Reliability

If SLCs are used for data storage, then reliability is improved, but storage capacity is reduced

Engineering Contradiction:
Improvedata reliabilityVSAvoidstorage capacity
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The system implements local quality differentiation by assigning SLC storage to data requiring high reliability (such as frequently accessed or critical data) and QLC storage to data with lower reliability requirements. This localized approach to reliability optimization allows the system to achieve high reliability for important data while maintaining overall high storage capacity through the use of QLC for less critical data.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The system dynamically reassesses reliability requirements and migrates data between SLC and QLC based on changing conditions. If data becomes more frequently accessed or more critical, it is automatically migrated to SLC for enhanced reliability. If reliability requirements decrease, data is migrated to QLC to optimize capacity utilization. This dynamic reliability management resolves the contradiction by matching storage medium characteristics to actual data requirements.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS12086466B2Implementing variable number of bits per cell on storage devices
Publication Date: 2024.09.10 MICRON TECHNOLOGY INC
  • US12086466B2 patent drawing
  • US12086466B2 patent drawing
  • US12086466B2 patent drawing

AI summary

Systems and methods are disclosed including a memory device and a processing device, operatively coupled with the memory device, to perform operations including programming first data to a set of memory cells of a first wordline using a first number of bits per memory cell. Responsive to receiving second data to program to the set of memory cells of the first wordline, the operations further include determining an error rate associated with a second wordline adjacent to the first wordline. Responsive to determining that the error rate satisfies a threshold criterion, the operations further include selecting a second number of bits per memory cell to program the second data to the first wordline and reprograming, using the second number of bits per memory cell, the first wordline storing the first data by programming second data to the set of memory cells while maintaining the first data.