Variable Branch Delay Slots in Pipelined Processors
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Solution Overview
Problem
In pipelined processor architectures, branch delay slots often require insertion of useless NOP instructions due to uncertainties in conditional branch and jump operations, leading to performance penalties and increased complexity in managing instruction flow and prediction logic.
Innovation Solution
A compiler/scheduler system that categorizes jump/branch instructions by their target address resolution stages and assigns variable numbers of delay slots based on when the target addresses can be resolved, allowing for execution of independent instructions in these slots, thereby minimizing the need for NOPs and optimizing pipeline utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If branch delay slots are used to keep the pipeline full, then processor performance is improved, but the number of useful instructions that can be executed is reduced due to uncertainty in branch outcomes
Solution Approach 1:
The patent applies dynamics by making the number of branch delay slots variable rather than fixed. The compiler/scheduler dynamically determines the number of delay slots based on when the branch target address can be resolved during pipeline execution. This allows the system to adapt the pipeline structure to the specific branch instruction characteristics, maximizing the number of useful instructions that can be executed without inserting NOPs.
2Ease of manufacture
If a fixed number of branch delay slots is used, then hardware design is simplified, but pipeline utilization is reduced due to insertion of NOP instructions
Solution Approach 1:
The patent changes the parameter of branch delay slot count from a fixed value to a variable determined by the compiler/scheduler. Different branch instructions can have different numbers of delay slots assigned based on their target address resolution timing. This parameter change allows the system to optimize pipeline utilization for each branch instruction while maintaining a relatively simple hardware architecture that can accommodate variable delay slot counts.
3Productivity
If branch prediction techniques are used to reduce delay slots, then processor performance is improved, but hardware complexity increases
Solution Approach 1:
The patent applies preliminary action by having the compiler/scheduler determine the number of branch delay slots at compile time based on static analysis of branch target address resolution stages. This preliminary determination eliminates the need for complex runtime branch prediction hardware, as the delay slot count is pre-calculated and embedded in the compiled code. The approach achieves performance improvement through software optimization rather than hardware complexity.
Data Source
AI summary
Different numbers of delay slots are assigned by a compiler/scheduler to each different type of jump operation in a pipelined processor system. The number of delay slots is variable and kept to the minimum needed by each type of jump operation. A compatible processor uses a corresponding number of branch delay slots to exploit the difference in predictability of different types of branch or jump operations. Different types of jump operations resolved their target addresses in different numbers of delay slots. As a result, the compiler/scheduler is able to generate more efficient code than for a processor with a fixed number of delay slots for all jump types, resulting in better processor performance.