Variable-Buffer Descriptor Fetching to Reduce Multi-Queue DMA Latency
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Solution Overview
Problem
Descriptor fetch operations in Multi-Queue Direct Memory Access (MQ-DMA) systems residing in host memory cause significant latency and reduced bandwidth due to the time required to fetch descriptors from these queues.
Innovation Solution
Implementing a descriptor fetch mechanism that includes indirect descriptor fetch using an index ring and descriptor table to coalesce multiple fetch operations into a single operation, and parallel processing of chain descriptors with variable buffer sizes, along with a prefetch mechanism to maintain a constant number of prefetched descriptors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If descriptors are fetched from descriptor queues residing in host memory, then the MQ-DMA system can track DMA operations accurately, but the descriptor fetch operations take significant time resulting in increased system latency and reduced bandwidth
Solution Approach 1:
The system performs preliminary actions by maintaining descriptor queues in host memory with proper organization and using descriptor rings that are pre-configured with descriptor information. This allows the MQ-DMA system to access descriptors more efficiently without compromising tracking accuracy, thereby reducing fetch latency while maintaining reliability
Solution Approach 2:
The patent introduces descriptor rings as an intermediary structure between the host memory and the MQ-DMA system. These rings act as a buffer layer that facilitates faster descriptor access while maintaining the accuracy of DMA operation tracking, thus resolving the contradiction between reliable tracking and fast access
2Reliability
If multiple descriptor fetch operations are performed sequentially from host memory, then each descriptor can be fetched accurately, but the overall bandwidth is reduced due to the time required for each fetch operation
Solution Approach 1:
The system merges multiple descriptor fetch operations into a single coherent access pattern using descriptor rings. By organizing descriptors in a ring structure that can be accessed sequentially or in batches, the system maintains fetch accuracy while significantly improving bandwidth utilization through reduced memory access overhead
Solution Approach 2:
The descriptor ring structure enables continuous descriptor fetch operations without interruption. The ring-based organization allows the MQ-DMA system to maintain a steady stream of descriptor accesses, ensuring both accuracy and high bandwidth utilization by eliminating gaps between fetch operations
3Ease of manufacture
If the system uses a fixed buffer size for descriptors, then memory allocation is simplified, but the system cannot efficiently handle variable-sized data packets resulting in wasted memory or insufficient buffering
Solution Approach 1:
The system implements dynamic buffer size allocation within the descriptor ring structure. Each descriptor in the ring can specify different buffer sizes based on the actual data packet requirements, allowing the system to maintain simple ring-based memory allocation while adapting to variable packet sizes. This dynamic approach enables efficient memory utilization without sacrificing allocation simplicity
Data Source
AI summary
Descriptor fetch for a direct memory access system includes, in response to receiving a first data packet, fetching a plurality of descriptors including a first descriptor and a specified number of prefetched descriptors. The plurality of descriptors specify different buffer sizes. In response to processing each data packet, selectively replenishing the plurality of fetched descriptors to the specified number of prefetched descriptors.