Variable Cache Memory Masking Logic for Integrated Circuit Design
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Solution Overview
Problem
Existing integrated circuit designs with variable cache memory sizes face challenges in validation efforts and cost due to the need for multiple cache size configurations, with redundant masking logic introducing timing delays and increasing integration testing complexity.
Innovation Solution
Incorporating masking logic within the cache memory to dynamically adjust address values based on cache size signals, allowing the cache controller to operate with various cache sizes while keeping the processor core design hardened and separate from cache memory, and using a software programmable register to configure cache sizes efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If user defined parameters are included in the cache controller design to specify cache size, then variable cache size is achieved, but validation effort and cost significantly increase
Solution Approach 1:
The patent separates the cache controller design from the cache memory size configuration. The cache controller is designed once with generic interfaces, while cache size-specific logic is segmented into separate cache memory modules. This segmentation allows the controller to be validated once and reused across multiple cache size configurations without increasing validation effort.
Solution Approach 2:
The cache controller is designed as a universal component that can work with multiple cache size configurations through standardized interfaces. The same controller design serves multiple functions across different cache sizes, eliminating the need to validate each configuration separately and reducing overall validation effort while maintaining adaptability.
2Adaptability or versatility
If masking logic is provided in the cache controller to support variable cache size, then flexibility is achieved, but redundant logic increases overhead and timing delay
Solution Approach 1:
The patent extracts the size-specific masking logic from the cache controller and relocates it to the cache memory module. This extraction removes redundant logic from the timing-critical cache controller path, eliminating unnecessary delays while preserving cache size flexibility through the relocated logic in the cache memory.
Solution Approach 2:
The cache memory interface acts as an intermediary between the cache controller and cache memory, handling size-specific masking operations. This intermediary approach allows the controller to operate with fixed, optimized timing while the interface translates generic controller commands into size-appropriate operations for the specific cache configuration.
3Adaptability or versatility
If masking logic is located in timing critical paths to enable variable cache size, then adaptability is achieved, but path delay increases
Solution Approach 1:
The masking logic is extracted from the timing-critical cache controller path and placed in the cache memory module. This relocation removes the source of delay from the critical access path, allowing the controller to operate at full speed while the extracted logic handles size-specific operations outside the timing constraint.
Solution Approach 2:
Cache size configuration is determined and configured in advance during system initialization or manufacturing, allowing the masking logic to be pre-configured for the specific cache size. This preliminary action eliminates the need for runtime masking decisions in the critical path, maintaining access speed while supporting variable cache sizes.
4Adaptability or versatility
If cache controller design is parameterized for different cache sizes, then variable configuration is achieved, but core design cannot be hardened and reused
Solution Approach 1:
The cache controller is designed as a universal, size-agnostic component with standardized interfaces that work with multiple cache configurations. This universal design can be hardened once and reused across different product families and cache sizes, improving ease of manufacture while maintaining adaptability through the interface layer.
Solution Approach 2:
The system is segmented into a universal cache controller portion and cache size-specific cache memory portions. The controller segment can be independently hardened and reused, while the cache memory segment is configured for specific sizes. This segmentation enables design reuse without sacrificing variable cache size capability.
Data Source
AI summary
An integrated circuit 2 is provided with a cache memory 6 and a cache controller 10 coupled to the cache memory 6 via a cache memory interface 8. The cache controller supports different cache memory sizes. The cache memory 6 includes masking logic 14 responsive to cache memory size signals to form masked address values for use in accessing the cache memory 6. The cache controller 10 can be part of a processor core 4 which may be hardened in its design and yet able to cope with variable cache memory sizes since the masking logic 14 is provided within the cache memory 6 outside of the hardened periphery of the processor core 4.